From fea04f795271db8fc56655bdade20174efca8fbb Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Mon, 20 May 2019 18:16:24 +0200 Subject: vhdl: properly group messages for overloading error. --- src/errorout.adb | 2 +- src/vhdl/vhdl-sem_expr.adb | 20 ++++++++++++++++++++ src/vhdl/vhdl-sem_names.adb | 6 ++++-- 3 files changed, 25 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/errorout.adb b/src/errorout.adb index d1bec4cbf..c00e46e05 100644 --- a/src/errorout.adb +++ b/src/errorout.adb @@ -383,7 +383,7 @@ package body Errorout is procedure Report_End_Group is begin - pragma Assert (In_Group > 1); + pragma Assert (In_Group > 0); In_Group := 0; Report_Handler.Message_Group.all (False); end Report_End_Group; diff --git a/src/vhdl/vhdl-sem_expr.adb b/src/vhdl/vhdl-sem_expr.adb index dfbf004e0..1129abdb7 100644 --- a/src/vhdl/vhdl-sem_expr.adb +++ b/src/vhdl/vhdl-sem_expr.adb @@ -1325,8 +1325,10 @@ package body Vhdl.Sem_Expr is if A_Type /= Null_Iir then -- Cannot find a single interpretation for a given -- type. + Report_Start_Group; Error_Overload (Expr); Disp_Overload_List (Imp_List, Expr); + Report_End_Group; return Null_Iir; end if; @@ -1341,16 +1343,20 @@ package body Vhdl.Sem_Expr is if Get_Nbr_Elements (Res_Type) = 1 then -- several implementations but one profile. + Report_Start_Group; Error_Overload (Expr); Disp_Overload_List (Imp_List, Expr); + Report_End_Group; return Null_Iir; end if; Set_Type (Expr, Create_Overload_List (Res_Type)); else -- For a procedure call, the context does't help to resolve -- overload. + Report_Start_Group; Error_Overload (Expr); Disp_Overload_List (Imp_List, Expr); + Report_End_Group; end if; return Expr; end case; @@ -1457,8 +1463,10 @@ package body Vhdl.Sem_Expr is /= Not_Compatible then if Res /= Null_Iir then + Report_Start_Group; Error_Overload (Expr); Disp_Overload_List (Overload_List, Expr); + Report_End_Group; return Null_Iir; else Res := Inter; @@ -1757,8 +1765,10 @@ package body Vhdl.Sem_Expr is -- Note: operator and implementation node of expr must be set. procedure Error_Operator_Overload (List : Iir_List) is begin + Report_Start_Group; Error_Msg_Sem (+Expr, "operator ""%i"" is overloaded", +Operator); Disp_Overload_List (List, Expr); + Report_End_Group; end Error_Operator_Overload; Interface_Chain : Iir; @@ -4959,10 +4969,12 @@ package body Vhdl.Sem_Expr is if Res /= Null_Iir and then Is_Overloaded (Res) then -- FIXME: clarify between overload and not determinable from the -- context. + Report_Start_Group; Error_Overload (Expr); if Get_Type (Res) /= Null_Iir then Disp_Overload_List (Get_Overload_List (Get_Type (Res)), Expr); end if; + Report_End_Group; return Null_Iir; end if; return Res; @@ -4996,8 +5008,10 @@ package body Vhdl.Sem_Expr is Error_Overload (Expr); return Null_Iir; elsif Is_Overload_List (Res_Type) then + Report_Start_Group; Error_Overload (Expr); Disp_Overload_List (Get_Overload_List (Res_Type), Expr); + Report_End_Group; Free_Overload_List (Res_Type); return Null_Iir; else @@ -5054,8 +5068,10 @@ package body Vhdl.Sem_Expr is end loop; if Res = Null_Iir then + Report_Start_Group; Error_Overload (Expr); Disp_Overload_List (Type_List, Expr); + Report_End_Group; return Null_Iir; end if; @@ -5126,16 +5142,20 @@ package body Vhdl.Sem_Expr is if Res = Null_Iir then Res := El; else + Report_Start_Group; Error_Overload (Expr1); Disp_Overload_List (List, Expr1); + Report_End_Group; return Null_Iir; end if; end if; Next (It); end loop; if Res = Null_Iir then + Report_Start_Group; Error_Overload (Expr1); Disp_Overload_List (List, Expr1); + Report_End_Group; return Null_Iir; end if; return Sem_Expression_Ov (Expr1, Get_Base_Type (Res)); diff --git a/src/vhdl/vhdl-sem_names.adb b/src/vhdl/vhdl-sem_names.adb index 32195d92f..c8ec40285 100644 --- a/src/vhdl/vhdl-sem_names.adb +++ b/src/vhdl/vhdl-sem_names.adb @@ -62,7 +62,6 @@ package body Vhdl.Sem_Names is El : Iir; It : List_Iterator; begin - Report_Start_Group; Error_Msg_Sem (+Loc, "possible interpretations are:"); It := List_Iterate (List); while Is_Valid (It) loop @@ -79,7 +78,6 @@ package body Vhdl.Sem_Names is end case; Next (It); end loop; - Report_End_Group; end Disp_Overload_List; -- Create an overload list. @@ -4049,8 +4047,10 @@ package body Vhdl.Sem_Names is Free_Iir (Res); Res := Res1; else + Report_Start_Group; Error_Overload (Name); Disp_Overload_List (Get_Overload_List (Res), Name); + Report_End_Group; Free_Iir (Res); return Create_Error_Expr (Name, A_Type); end if; @@ -4077,8 +4077,10 @@ package body Vhdl.Sem_Names is else -- There is either no types or one type for -- several meanings. + Report_Start_Group; Error_Overload (Name); Disp_Overload_List (Expr_List, Name); + Report_End_Group; --Free_Iir (Ret_Type); return Create_Error_Expr (Name, A_Type); end if; -- cgit v1.2.3