From fe6edccd9c03f40878cc1d27b07c024407d63bff Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Thu, 18 Aug 2022 06:21:17 +0200
Subject: ghdlsimul: add an option to debug before elaboration

---
 src/ghdldrv/ghdlsimul.adb      | 2 ++
 src/simul/simul-vhdl_simul.adb | 6 +++---
 src/simul/simul-vhdl_simul.ads | 1 +
 3 files changed, 6 insertions(+), 3 deletions(-)

(limited to 'src')

diff --git a/src/ghdldrv/ghdlsimul.adb b/src/ghdldrv/ghdlsimul.adb
index ae8a6d4b4..a2c1d3ca2 100644
--- a/src/ghdldrv/ghdlsimul.adb
+++ b/src/ghdldrv/ghdlsimul.adb
@@ -179,6 +179,8 @@ package body Ghdlsimul is
          Synth.Flags.Flag_Trace_Statements := True;
       elsif Option = "-i" then
          Simul.Vhdl_Simul.Flag_Interractive := True;
+      elsif Option = "-ge" then
+         Simul.Vhdl_Simul.Flag_Debug_Elab := True;
       else
          return False;
       end if;
diff --git a/src/simul/simul-vhdl_simul.adb b/src/simul/simul-vhdl_simul.adb
index b44028c57..5d691e807 100644
--- a/src/simul/simul-vhdl_simul.adb
+++ b/src/simul/simul-vhdl_simul.adb
@@ -2075,9 +2075,9 @@ package body Simul.Vhdl_Simul is
 
 --      Grt.Errors.Error_Hook := Debug_Error'Access;
 
---      if Flag_Interractive then
---         Debug (Reason_Start);
---      end if;
+      if Flag_Debug_Elab then
+         Elab.Debugger.Debug_Elab (Vhdl_Elab.Top_Instance);
+      end if;
 
       Ok := Grt.Main.Run_Elab;
       if not Ok then
diff --git a/src/simul/simul-vhdl_simul.ads b/src/simul/simul-vhdl_simul.ads
index 5e837d454..a929c3fa6 100644
--- a/src/simul/simul-vhdl_simul.ads
+++ b/src/simul/simul-vhdl_simul.ads
@@ -37,6 +37,7 @@ package Simul.Vhdl_Simul is
    Trace_Simulation : Boolean := False;
 
    Flag_Interractive : Boolean := False;
+   Flag_Debug_Elab : Boolean := False;
 
    Trace_Residues : Boolean := False;
 
-- 
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