From bb357cf03c7e956db1539712fd64353b6d87872d Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Fri, 10 Jun 2022 06:36:49 +0200 Subject: vhdl: recognize ieee.math_real.sign, fix is_x recogn. --- src/std_names.adb | 1 + src/std_names.ads | 13 +++++++------ src/synth/synth-vhdl_eval.adb | 25 +++++++++++++++++++++---- src/synth/synth-vhdl_oper.adb | 4 ++-- src/vhdl/vhdl-ieee-math_real.adb | 2 ++ src/vhdl/vhdl-ieee-std_logic_1164.adb | 20 ++++++++++++++++---- src/vhdl/vhdl-nodes.ads | 4 ++-- 7 files changed, 51 insertions(+), 18 deletions(-) (limited to 'src') diff --git a/src/std_names.adb b/src/std_names.adb index 649029ff7..fe0038318 100644 --- a/src/std_names.adb +++ b/src/std_names.adb @@ -678,6 +678,7 @@ package body Std_Names is Def ("sin", Name_Sin); Def ("cos", Name_Cos); Def ("arctan", Name_Arctan); + Def ("sign", Name_Sign); Def ("shl", Name_Shl); Def ("shr", Name_Shr); Def ("ext", Name_Ext); diff --git a/src/std_names.ads b/src/std_names.ads index d27494d26..7b6711c98 100644 --- a/src/std_names.ads +++ b/src/std_names.ads @@ -762,12 +762,13 @@ package Std_Names is Name_Sin : constant Name_Id := Name_First_Ieee_Name + 043; Name_Cos : constant Name_Id := Name_First_Ieee_Name + 044; Name_Arctan : constant Name_Id := Name_First_Ieee_Name + 045; - Name_Shl : constant Name_Id := Name_First_Ieee_Name + 046; - Name_Shr : constant Name_Id := Name_First_Ieee_Name + 047; - Name_Ext : constant Name_Id := Name_First_Ieee_Name + 048; - Name_Sxt : constant Name_Id := Name_First_Ieee_Name + 049; - Name_Find_Leftmost : constant Name_Id := Name_First_Ieee_Name + 050; - Name_Find_Rightmost : constant Name_Id := Name_First_Ieee_Name + 051; + Name_Sign : constant Name_Id := Name_First_Ieee_Name + 046; + Name_Shl : constant Name_Id := Name_First_Ieee_Name + 047; + Name_Shr : constant Name_Id := Name_First_Ieee_Name + 048; + Name_Ext : constant Name_Id := Name_First_Ieee_Name + 049; + Name_Sxt : constant Name_Id := Name_First_Ieee_Name + 050; + Name_Find_Leftmost : constant Name_Id := Name_First_Ieee_Name + 051; + Name_Find_Rightmost : constant Name_Id := Name_First_Ieee_Name + 052; Name_Last_Ieee_Name : constant Name_Id := Name_Find_Rightmost; Name_First_Synthesis : constant Name_Id := Name_Last_Ieee_Name + 1; diff --git a/src/synth/synth-vhdl_eval.adb b/src/synth/synth-vhdl_eval.adb index 8ffbf5c4f..96564be6a 100644 --- a/src/synth/synth-vhdl_eval.adb +++ b/src/synth/synth-vhdl_eval.adb @@ -2223,10 +2223,12 @@ package body Synth.Vhdl_Eval is | Iir_Predefined_Ieee_Numeric_Std_To_X01_Sgn => return Eval_To_X01 (Get_Memtyp (Param1), Map_X01); when Iir_Predefined_Ieee_Numeric_Std_To_X01Z_Uns - | Iir_Predefined_Ieee_Numeric_Std_To_X01Z_Sgn => + | Iir_Predefined_Ieee_Numeric_Std_To_X01Z_Sgn + | Iir_Predefined_Ieee_1164_To_X01Z_Slv => return Eval_To_X01 (Get_Memtyp (Param1), Map_X01Z); when Iir_Predefined_Ieee_Numeric_Std_To_UX01_Uns - | Iir_Predefined_Ieee_Numeric_Std_To_UX01_Sgn => + | Iir_Predefined_Ieee_Numeric_Std_To_UX01_Sgn + | Iir_Predefined_Ieee_1164_To_UX01_Slv => return Eval_To_X01 (Get_Memtyp (Param1), Map_UX01); when Iir_Predefined_Ieee_1164_To_Stdlogicvector_Bv @@ -2310,7 +2312,7 @@ package body Synth.Vhdl_Eval is return Res; end; - when Iir_Predefined_Ieee_1164_Scalar_Is_X => + when Iir_Predefined_Ieee_1164_Is_X_Log => declare B : Std_Ulogic; begin @@ -2320,7 +2322,8 @@ package body Synth.Vhdl_Eval is end; when Iir_Predefined_Ieee_Numeric_Std_Is_X_Uns - | Iir_Predefined_Ieee_Numeric_Std_Is_X_Sgn => + | Iir_Predefined_Ieee_Numeric_Std_Is_X_Sgn + | Iir_Predefined_Ieee_1164_Is_X_Slv => declare Len : constant Uns32 := Param1.Typ.Abound.Len; Res : Boolean; @@ -2392,6 +2395,20 @@ package body Synth.Vhdl_Eval is return Minmax (Get_Memtyp (Param1), Get_Memtyp (Param2), False, False); + when Iir_Predefined_Ieee_Math_Real_Sign => + declare + Val : constant Fp64 := Read_Fp64 (Param1); + Res : Fp64; + begin + if Val > 0.0 then + Res := 1.0; + elsif Val < 0.0 then + Res := -1.0; + else + Res := 0.0; + end if; + return Create_Memory_Fp64 (Res, Res_Typ); + end; when Iir_Predefined_Ieee_Math_Real_Log2 => declare function Log2 (Arg : Fp64) return Fp64; diff --git a/src/synth/synth-vhdl_oper.adb b/src/synth/synth-vhdl_oper.adb index a60e9b295..919d1f64e 100644 --- a/src/synth/synth-vhdl_oper.adb +++ b/src/synth/synth-vhdl_oper.adb @@ -1958,8 +1958,8 @@ package body Synth.Vhdl_Oper is Set_Location (Edge, Expr); return Create_Value_Net (Edge, Res_Typ); end; - when Iir_Predefined_Ieee_1164_Scalar_Is_X - | Iir_Predefined_Ieee_1164_Vector_Is_X => + when Iir_Predefined_Ieee_1164_Is_X_Log + | Iir_Predefined_Ieee_1164_Is_X_Slv => -- Always false. return Create_Value_Discrete (0, Boolean_Type); when Iir_Predefined_Ieee_1164_To_Bitvector diff --git a/src/vhdl/vhdl-ieee-math_real.adb b/src/vhdl/vhdl-ieee-math_real.adb index 1881bb322..d52b8ae85 100644 --- a/src/vhdl/vhdl-ieee-math_real.adb +++ b/src/vhdl/vhdl-ieee-math_real.adb @@ -40,6 +40,8 @@ package body Vhdl.Ieee.Math_Real is when Iir_Kind_Function_Declaration => Def := Iir_Predefined_None; case Get_Identifier (Decl) is + when Name_Sign => + Def := Iir_Predefined_Ieee_Math_Real_Sign; when Name_Mod => Def := Iir_Predefined_Ieee_Math_Real_Mod; when Name_Ceil => diff --git a/src/vhdl/vhdl-ieee-std_logic_1164.adb b/src/vhdl/vhdl-ieee-std_logic_1164.adb index ff2d95190..207d2f0c5 100644 --- a/src/vhdl/vhdl-ieee-std_logic_1164.adb +++ b/src/vhdl/vhdl-ieee-std_logic_1164.adb @@ -383,6 +383,20 @@ package body Vhdl.Ieee.Std_Logic_1164 is elsif Is_Scalar_Function (Decl) then Predefined := Iir_Predefined_Ieee_1164_To_X01_Log; end if; + when Name_To_UX01 => + if Is_Vector_Function (Decl) then + -- TODO: distinguish slv/suv. + Predefined := Iir_Predefined_Ieee_1164_To_UX01_Slv; + elsif Is_Scalar_Function (Decl) then + Predefined := Iir_Predefined_Ieee_1164_To_UX01_Log; + end if; + when Name_To_X01Z => + if Is_Vector_Function (Decl) then + -- TODO: distinguish slv/suv. + Predefined := Iir_Predefined_Ieee_1164_To_X01Z_Slv; + elsif Is_Scalar_Function (Decl) then + Predefined := Iir_Predefined_Ieee_1164_To_X01Z_Log; + end if; when Name_To_Hstring => Predefined := Iir_Predefined_Ieee_1164_To_Hstring; when Name_To_Ostring => @@ -413,8 +427,7 @@ package body Vhdl.Ieee.Std_Logic_1164 is Predefined := Iir_Predefined_Ieee_1164_Condition_Operator; when Name_Is_X => - Predefined := - Iir_Predefined_Ieee_1164_Scalar_Is_X; + Predefined := Iir_Predefined_Ieee_1164_Is_X_Log; when others => Predefined := Iir_Predefined_None; end case; @@ -452,8 +465,7 @@ package body Vhdl.Ieee.Std_Logic_1164 is when Name_Xnor => Predefined := Iir_Predefined_Ieee_1164_Xnor_Suv; when Name_Is_X => - Predefined := - Iir_Predefined_Ieee_1164_Scalar_Is_X; + Predefined := Iir_Predefined_Ieee_1164_Is_X_Slv; when others => Predefined := Iir_Predefined_None; end case; diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads index f9b29cf78..c1868bfc7 100644 --- a/src/vhdl/vhdl-nodes.ads +++ b/src/vhdl/vhdl-nodes.ads @@ -5669,8 +5669,8 @@ package Vhdl.Nodes is Iir_Predefined_Ieee_1164_To_UX01_Bv_Suv, Iir_Predefined_Ieee_1164_To_UX01_Bit_Log, - Iir_Predefined_Ieee_1164_Vector_Is_X, - Iir_Predefined_Ieee_1164_Scalar_Is_X, + Iir_Predefined_Ieee_1164_Is_X_Slv, + Iir_Predefined_Ieee_1164_Is_X_Log, Iir_Predefined_Ieee_1164_Rising_Edge, Iir_Predefined_Ieee_1164_Falling_Edge, -- cgit v1.2.3