From afaf45e1da10e91cbab6856b1b97203b9f7c7e99 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Mon, 18 Jul 2016 07:01:04 +0200 Subject: Improve error message if synopsys package it not found. --- src/std_names.adb | 25 ++++++++++++++----------- src/std_names.ads | 29 ++++++++++++++++------------- src/vhdl/sem_names.adb | 26 +++++++++++++++++++++++--- 3 files changed, 53 insertions(+), 27 deletions(-) (limited to 'src') diff --git a/src/std_names.adb b/src/std_names.adb index c9338396c..e67acaa04 100644 --- a/src/std_names.adb +++ b/src/std_names.adb @@ -400,17 +400,20 @@ package body Std_Names is Def ("get_resolution_limit", Name_Get_Resolution_Limit); Def ("control_simulation", Name_Control_Simulation); - Def ("ieee", Name_Ieee); - Def ("std_logic_1164", Name_Std_Logic_1164); - Def ("std_ulogic", Name_Std_Ulogic); - Def ("std_ulogic_vector", Name_Std_Ulogic_Vector); - Def ("std_logic", Name_Std_Logic); - Def ("std_logic_vector", Name_Std_Logic_Vector); - Def ("rising_edge", Name_Rising_Edge); - Def ("falling_edge", Name_Falling_Edge); - Def ("vital_timing", Name_VITAL_Timing); - Def ("vital_level0", Name_VITAL_Level0); - Def ("vital_level1", Name_VITAL_Level1); + Def ("ieee", Name_Ieee); + Def ("std_logic_1164", Name_Std_Logic_1164); + Def ("std_ulogic", Name_Std_Ulogic); + Def ("std_ulogic_vector", Name_Std_Ulogic_Vector); + Def ("std_logic", Name_Std_Logic); + Def ("std_logic_vector", Name_Std_Logic_Vector); + Def ("rising_edge", Name_Rising_Edge); + Def ("falling_edge", Name_Falling_Edge); + Def ("vital_timing", Name_VITAL_Timing); + Def ("vital_level0", Name_VITAL_Level0); + Def ("vital_level1", Name_VITAL_Level1); + Def ("std_logic_arith", Name_Std_Logic_Arith); + Def ("std_logic_signed", Name_Std_Logic_Signed); + Def ("std_logic_unsigned", Name_Std_Logic_Unsigned); -- Verilog keywords Def ("always", Name_Always); diff --git a/src/std_names.ads b/src/std_names.ads index d830499a6..b63762072 100644 --- a/src/std_names.ads +++ b/src/std_names.ads @@ -469,19 +469,22 @@ package Std_Names is Name_Control_Simulation : constant Name_Id := Name_First_Misc + 026; Name_Last_Misc : constant Name_Id := Name_Control_Simulation; - Name_First_Ieee : constant Name_Id := Name_Last_Misc + 1; - Name_Ieee : constant Name_Id := Name_First_Ieee + 000; - Name_Std_Logic_1164 : constant Name_Id := Name_First_Ieee + 001; - Name_Std_Ulogic : constant Name_Id := Name_First_Ieee + 002; - Name_Std_Ulogic_Vector : constant Name_Id := Name_First_Ieee + 003; - Name_Std_Logic : constant Name_Id := Name_First_Ieee + 004; - Name_Std_Logic_Vector : constant Name_Id := Name_First_Ieee + 005; - Name_Rising_Edge : constant Name_Id := Name_First_Ieee + 006; - Name_Falling_Edge : constant Name_Id := Name_First_Ieee + 007; - Name_VITAL_Timing : constant Name_Id := Name_First_Ieee + 008; - Name_VITAL_Level0 : constant Name_Id := Name_First_Ieee + 009; - Name_VITAL_Level1 : constant Name_Id := Name_First_Ieee + 010; - Name_Last_Ieee : constant Name_Id := Name_VITAL_Level1; + Name_First_Ieee : constant Name_Id := Name_Last_Misc + 1; + Name_Ieee : constant Name_Id := Name_First_Ieee + 000; + Name_Std_Logic_1164 : constant Name_Id := Name_First_Ieee + 001; + Name_Std_Ulogic : constant Name_Id := Name_First_Ieee + 002; + Name_Std_Ulogic_Vector : constant Name_Id := Name_First_Ieee + 003; + Name_Std_Logic : constant Name_Id := Name_First_Ieee + 004; + Name_Std_Logic_Vector : constant Name_Id := Name_First_Ieee + 005; + Name_Rising_Edge : constant Name_Id := Name_First_Ieee + 006; + Name_Falling_Edge : constant Name_Id := Name_First_Ieee + 007; + Name_VITAL_Timing : constant Name_Id := Name_First_Ieee + 008; + Name_VITAL_Level0 : constant Name_Id := Name_First_Ieee + 009; + Name_VITAL_Level1 : constant Name_Id := Name_First_Ieee + 010; + Name_Std_Logic_Arith : constant Name_Id := Name_First_Ieee + 011; + Name_Std_Logic_Signed : constant Name_Id := Name_First_Ieee + 012; + Name_Std_Logic_Unsigned : constant Name_Id := Name_First_Ieee + 013; + Name_Last_Ieee : constant Name_Id := Name_Std_Logic_Unsigned; -- Verilog keywords. Name_First_Verilog : constant Name_Id := Name_Last_Ieee + 1; diff --git a/src/vhdl/sem_names.adb b/src/vhdl/sem_names.adb index fdb6c4fbc..006390332 100644 --- a/src/vhdl/sem_names.adb +++ b/src/vhdl/sem_names.adb @@ -1887,6 +1887,28 @@ package body Sem_Names is ("no method " & Name_Table.Image (Suffix) & " in " & Disp_Node (Prot_Type), Name); end Error_Protected_Item; + + -- Emit an error message if unit is not found in library LIB. + procedure Error_Unit_Not_Found (Lib : Iir) + is + use Std_Names; + begin + Error_Msg_Sem + ("unit """ & Name_Table.Image (Suffix) + & """ not found in " & Disp_Node (Lib), Name); + + -- Give an advice for common synopsys packages. + if Get_Identifier (Lib) = Name_Ieee then + if Suffix = Name_Std_Logic_Arith + or else Suffix = Name_Std_Logic_Signed + or else Suffix = Name_Std_Logic_Unsigned + then + Error_Msg_Sem + (" (use --ieee=synopsys for non-standard synopsys packages)", + Name); + end if; + end if; + end Error_Unit_Not_Found; begin -- Analyze prefix. Sem_Name (Prefix_Name); @@ -1954,9 +1976,7 @@ package body Sem_Names is -- GHDL: FIXME: error message more explicit Res := Libraries.Load_Primary_Unit (Prefix, Suffix, Name); if Res = Null_Iir then - Error_Msg_Sem - ("primary unit """ & Name_Table.Image (Suffix) - & """ not found in " & Disp_Node (Prefix), Name); + Error_Unit_Not_Found (Prefix); else Sem.Add_Dependence (Res); Res := Get_Library_Unit (Res); -- cgit v1.2.3