From 902df03a4cdcbcfaca9379e68fb52062aeaeb7ca Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Wed, 11 Jan 2023 19:08:39 +0100
Subject: synth: use same wording for direction mismatch as simulation

---
 src/synth/synth-vhdl_expr.adb | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/synth/synth-vhdl_expr.adb b/src/synth/synth-vhdl_expr.adb
index ec0cd28bb..56ecbb310 100644
--- a/src/synth/synth-vhdl_expr.adb
+++ b/src/synth/synth-vhdl_expr.adb
@@ -1223,7 +1223,8 @@ package body Synth.Vhdl_Expr is
       Len : Uns32;
    begin
       if Pfx_Bnd.Dir /= Dir then
-         Error_Msg_Synth (Syn_Inst, Name, "direction mismatch in slice");
+         Error_Msg_Synth (Syn_Inst, Name,
+                          "slice direction doesn't match index direction");
          Off := (0, 0);
          if Dir = Dir_To then
             Res_Bnd := (Dir => Dir_To, Left => 1, Right => 0, Len => 0);
-- 
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