From 8eea89ff1969a28e2360c7240a1f9c37326d8fa5 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Thu, 5 Dec 2019 22:35:16 +0100 Subject: netlists-disp_vhdl: handle 1-bit add/sub. --- src/synth/netlists-disp_vhdl.adb | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) (limited to 'src') diff --git a/src/synth/netlists-disp_vhdl.adb b/src/synth/netlists-disp_vhdl.adb index 763a08f29..c063c7425 100644 --- a/src/synth/netlists-disp_vhdl.adb +++ b/src/synth/netlists-disp_vhdl.adb @@ -902,11 +902,19 @@ package body Netlists.Disp_Vhdl is Disp_X_Lit (Get_Width (Get_Output (Inst, 0))); Put_Line (" when others;"); when Id_Add => - Disp_Template (" \o0 <= std_logic_vector (\ui0 + \ui1);" & NL, - Inst); + if Get_Width (Get_Output (Inst, 0)) = 1 then + Disp_Template (" \o0 <= \i0 xor \i1; -- add" & NL, Inst); + else + Disp_Template (" \o0 <= std_logic_vector (\ui0 + \ui1);" & NL, + Inst); + end if; when Id_Sub => - Disp_Template (" \o0 <= std_logic_vector (\ui0 - \ui1);" & NL, - Inst); + if Get_Width (Get_Output (Inst, 0)) = 1 then + Disp_Template (" \o0 <= \i0 xor \i1; -- sub" & NL, Inst); + else + Disp_Template (" \o0 <= std_logic_vector (\ui0 - \ui1);" & NL, + Inst); + end if; when Id_Umul => Disp_Template (" \o0 <= std_logic_vector (resize (\ui0 * \ui1, \n0));" & NL, -- cgit v1.2.3