From 8c55533f130157e826c94a92f55200b916d980f5 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Tue, 17 May 2022 06:11:22 +0200 Subject: synth-vhdl_oper: handle to_stdulogicvector for slv. Fix #2062 --- src/synth/synth-vhdl_oper.adb | 1 + 1 file changed, 1 insertion(+) (limited to 'src') diff --git a/src/synth/synth-vhdl_oper.adb b/src/synth/synth-vhdl_oper.adb index 640a65b77..813a5513d 100644 --- a/src/synth/synth-vhdl_oper.adb +++ b/src/synth/synth-vhdl_oper.adb @@ -1937,6 +1937,7 @@ package body Synth.Vhdl_Oper is when Iir_Predefined_Ieee_1164_To_Bitvector | Iir_Predefined_Ieee_1164_To_Stdlogicvector_Suv | Iir_Predefined_Ieee_1164_To_Stdlogicvector_Bv + | Iir_Predefined_Ieee_1164_To_Stdulogicvector_Slv | Iir_Predefined_Ieee_1164_To_Stdulogicvector_Bv | Iir_Predefined_Ieee_Numeric_Std_To_01_Uns | Iir_Predefined_Ieee_Numeric_Std_To_01_Sgn -- cgit v1.2.3