From 7e89ed2b5108163d52788927fe49b0c5686adbd6 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Tue, 28 Jun 2022 02:42:05 +0200 Subject: netlists-disp_verilog: adjust, discard null signals. For #2113 --- src/synth/netlists-disp_verilog.adb | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/synth/netlists-disp_verilog.adb b/src/synth/netlists-disp_verilog.adb index 47fa0047a..cd13a6d77 100644 --- a/src/synth/netlists-disp_verilog.adb +++ b/src/synth/netlists-disp_verilog.adb @@ -444,9 +444,14 @@ package body Netlists.Disp_Verilog is -- a name. In that case, a signal will be created and driven. function Need_Signal (Inst : Instance) return Boolean is + O : constant Net := Get_Output (Inst, 0); I : Input; begin - I := Get_First_Sink (Get_Output (Inst, 0)); + if not Flag_Null_Wires and then Get_Width (O) = 0 then + return False; + end if; + + I := Get_First_Sink (O); while I /= No_Input loop if Need_Name (Get_Input_Parent (I)) then return True; -- cgit v1.2.3