From 612d41653c059b108df02d4ced4fbcfb37333183 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Fri, 30 Aug 2019 03:33:25 +0200
Subject: vhdl: recognize 1164 condition operator, handle in synth.

---
 src/synth/synth-expr.adb              |  2 ++
 src/vhdl/vhdl-ieee-std_logic_1164.adb | 20 +++++++++++++++-----
 src/vhdl/vhdl-nodes.ads               |  2 ++
 3 files changed, 19 insertions(+), 5 deletions(-)

(limited to 'src')

diff --git a/src/synth/synth-expr.adb b/src/synth/synth-expr.adb
index 5c6f957c7..d24486f3d 100644
--- a/src/synth/synth-expr.adb
+++ b/src/synth/synth-expr.adb
@@ -1388,6 +1388,8 @@ package body Synth.Expr is
             return Synth_Vec_Reduce_Monadic(Id_Red_And);
          when Iir_Predefined_Ieee_1164_Vector_Or_Reduce =>
             return Synth_Vec_Reduce_Monadic(Id_Red_Or);
+         when Iir_Predefined_Ieee_1164_Condition_Operator =>
+            return Operand;
          when others =>
             Error_Msg_Synth
               (+Loc,
diff --git a/src/vhdl/vhdl-ieee-std_logic_1164.adb b/src/vhdl/vhdl-ieee-std_logic_1164.adb
index 14468e1c4..7ea7da787 100644
--- a/src/vhdl/vhdl-ieee-std_logic_1164.adb
+++ b/src/vhdl/vhdl-ieee-std_logic_1164.adb
@@ -250,11 +250,21 @@ package body Vhdl.Ieee.Std_Logic_1164 is
                   end case;
                   Set_Implicit_Definition (Decl, Predefined);
                end;
-            elsif Is_Scalar_Function (Decl)
-              and then Get_Identifier (Decl) = Name_Not
-            then
-               Set_Implicit_Definition
-                 (Decl, Iir_Predefined_Ieee_1164_Scalar_Not);
+            elsif Is_Scalar_Function (Decl) then
+               declare
+                  Predefined : Iir_Predefined_Functions;
+               begin
+                  case Get_Identifier (Decl) is
+                     when Name_Not =>
+                        Predefined := Iir_Predefined_Ieee_1164_Scalar_Not;
+                     when Name_Op_Condition =>
+                        Predefined :=
+                          Iir_Predefined_Ieee_1164_Condition_Operator;
+                     when others =>
+                        Predefined := Iir_Predefined_None;
+                  end case;
+                  Set_Implicit_Definition (Decl, Predefined);
+               end;
             elsif Is_Vector_Vector_Function (Decl) then
                declare
                   Predefined : Iir_Predefined_Functions;
diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads
index 41ef5fd9e..a0cd6b429 100644
--- a/src/vhdl/vhdl-nodes.ads
+++ b/src/vhdl/vhdl-nodes.ads
@@ -4905,6 +4905,8 @@ package Vhdl.Nodes is
       Iir_Predefined_Ieee_1164_Vector_And_Reduce,
       Iir_Predefined_Ieee_1164_Vector_Or_Reduce,
 
+      Iir_Predefined_Ieee_1164_Condition_Operator,
+
       --  Numeric_Std.
       --  Abbreviations:
       --  Uns: Unsigned, Sgn: Signed, Nat: Natural, Int: Integer.
-- 
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