From 485b8f6b0260f5c0a72b8d6c42ad76c52fd889a1 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Tue, 13 Aug 2019 22:19:48 +0200 Subject: vhdl-nodes_walk: handle iir_kind_psl_default_clock. --- src/vhdl/vhdl-nodes_walk.adb | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/vhdl/vhdl-nodes_walk.adb b/src/vhdl/vhdl-nodes_walk.adb index 0bbddef3b..7a539a030 100644 --- a/src/vhdl/vhdl-nodes_walk.adb +++ b/src/vhdl/vhdl-nodes_walk.adb @@ -157,7 +157,8 @@ package body Vhdl.Nodes_Walk is while Is_Valid (El) loop case Iir_Kinds_Concurrent_Statement (Get_Kind (El)) is when Iir_Kinds_Simple_Concurrent_Statement - | Iir_Kind_Component_Instantiation_Statement => + | Iir_Kind_Component_Instantiation_Statement + | Iir_Kind_Psl_Default_Clock => Status := Cb.all (El); when Iir_Kind_Block_Statement => Status := Cb.all (El); -- cgit v1.2.3