From 3d35074b10658634d0e1a280575fa6af0b08730f Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Sun, 6 Oct 2019 13:08:09 +0200 Subject: netlists: remove renaming of Get_Parent for Net. --- src/synth/netlists-concats.adb | 4 ++-- src/synth/netlists-disp_vhdl.adb | 9 +++++---- src/synth/netlists-dump.adb | 8 ++++---- src/synth/netlists-locations.adb | 5 +++-- src/synth/netlists.adb | 2 +- src/synth/netlists.ads | 1 - src/synth/synth-environment-debug.adb | 4 ++-- src/synth/synth-environment.adb | 6 +++--- src/synth/synth-expr.adb | 10 +++++----- src/synth/synth-inference.adb | 8 ++++---- src/synth/synth-source.adb | 2 +- src/synth/synth-stmts.adb | 8 ++++---- 12 files changed, 34 insertions(+), 33 deletions(-) (limited to 'src') diff --git a/src/synth/netlists-concats.adb b/src/synth/netlists-concats.adb index b01308514..c833531b5 100644 --- a/src/synth/netlists-concats.adb +++ b/src/synth/netlists-concats.adb @@ -62,7 +62,7 @@ package body Netlists.Concats is end loop; N := Build_Concatn (Ctxt, Wd, Uns32 (C.Len)); - Inst := Get_Parent (N); + Inst := Get_Net_Parent (N); for I in 1 .. C.Len loop Connect (Get_Input (Inst, Port_Idx (I - 1)), C.Sarr (I)); end loop; @@ -74,7 +74,7 @@ package body Netlists.Concats is end loop; N := Build_Concatn (Ctxt, Wd, Uns32 (C.Len)); - Inst := Get_Parent (N); + Inst := Get_Net_Parent (N); for I in Net_Tables.First .. C.Len loop Connect (Get_Input (Inst, Port_Idx (I - 1)), C.Darr.Table (I)); end loop; diff --git a/src/synth/netlists-disp_vhdl.adb b/src/synth/netlists-disp_vhdl.adb index a2c751ad1..6bf6701a5 100644 --- a/src/synth/netlists-disp_vhdl.adb +++ b/src/synth/netlists-disp_vhdl.adb @@ -145,7 +145,7 @@ package body Netlists.Disp_Vhdl is end if; declare - Inst : constant Instance := Get_Parent (N); + Inst : constant Instance := Get_Net_Parent (N); Idx : constant Port_Idx := Get_Port_Idx (N); Inst_Name : Sname; Port_Name : Sname; @@ -429,7 +429,7 @@ package body Netlists.Disp_Vhdl is return; end if; - Net_Inst := Get_Parent (N); + Net_Inst := Get_Net_Parent (N); if Flag_Merge_Lit and then Is_Const_Module (Get_Id (Net_Inst)) and then not Need_Name (Inst) @@ -679,7 +679,8 @@ package body Netlists.Disp_Vhdl is Put (" process ("); First := True; for I in Iarr'Range loop - if Get_Id (Get_Parent (Iarr (I))) not in Constant_Module_Id + if (Get_Id (Get_Net_Parent (Iarr (I))) + not in Constant_Module_Id) then if First then First := False; @@ -955,7 +956,7 @@ package body Netlists.Disp_Vhdl is when Id_Idff => Put (" := "); Disp_Constant_Inline - (Get_Parent (Get_Input_Net (Inst, 2))); + (Get_Net_Parent (Get_Input_Net (Inst, 2))); when Constant_Module_Id => Put (" := "); Disp_Constant_Inline (Inst); diff --git a/src/synth/netlists-dump.adb b/src/synth/netlists-dump.adb index 385d72f22..7b7c6615c 100644 --- a/src/synth/netlists-dump.adb +++ b/src/synth/netlists-dump.adb @@ -100,7 +100,7 @@ package body Netlists.Dump is procedure Dump_Net_Name (N : Net; With_Id : Boolean := False) is - Inst : constant Instance := Get_Parent (N); + Inst : constant Instance := Get_Net_Parent (N); Idx : constant Port_Idx := Get_Port_Idx (N); begin Dump_Name (Get_Instance_Name (Inst)); @@ -285,7 +285,7 @@ package body Netlists.Dump is Put ("?"); else declare - Inst : constant Instance := Get_Parent (N); + Inst : constant Instance := Get_Net_Parent (N); Idx : constant Port_Idx := Get_Port_Idx (N); begin if Is_Self_Instance (Inst) then @@ -335,7 +335,7 @@ package body Netlists.Dump is if Drv = No_Net then Put ('?'); else - Drv_Inst := Get_Parent (Drv); + Drv_Inst := Get_Net_Parent (Drv); if Flag_Disp_Inline and then Can_Inline (Drv_Inst) then Disp_Instance (Drv_Inst, False); else @@ -350,7 +350,7 @@ package body Netlists.Dump is if N = No_Net then Put ('?'); else - Disp_Instance (Get_Parent (N), False); + Disp_Instance (Get_Net_Parent (N), False); end if; New_Line; end Debug_Net; diff --git a/src/synth/netlists-locations.adb b/src/synth/netlists-locations.adb index ecc1d42fd..c651fc752 100644 --- a/src/synth/netlists-locations.adb +++ b/src/synth/netlists-locations.adb @@ -67,12 +67,13 @@ package body Netlists.Locations is procedure Copy_Location1 (Dest : Net; Src : Instance) is begin - Set_Location (Get_Parent (Dest), Get_Location (Src)); + Set_Location (Get_Net_Parent (Dest), Get_Location (Src)); end Copy_Location1; procedure Copy_Location1 (Dest : Net; Src : Net) is begin - Set_Location (Get_Parent (Dest), Get_Location (Get_Parent (Src))); + Set_Location (Get_Net_Parent (Dest), + Get_Location (Get_Net_Parent (Src))); end Copy_Location1; procedure Copy_Location (Dest : Net; Src : Net) is diff --git a/src/synth/netlists.adb b/src/synth/netlists.adb index 4d1516510..c22302716 100644 --- a/src/synth/netlists.adb +++ b/src/synth/netlists.adb @@ -527,7 +527,7 @@ package body Netlists is function Get_Port_Idx (O : Net) return Port_Idx is pragma Assert (Is_Valid (O)); - Parent : constant Instance := Get_Parent (O); + Parent : constant Instance := Get_Net_Parent (O); begin return Port_Idx (O - Instances_Table.Table (Parent).First_Output); end Get_Port_Idx; diff --git a/src/synth/netlists.ads b/src/synth/netlists.ads index 8fa1d3fad..def0e12b8 100644 --- a/src/synth/netlists.ads +++ b/src/synth/netlists.ads @@ -264,7 +264,6 @@ package Netlists is -- Net (Output) function Get_Net_Parent (O : Net) return Instance; - function Get_Parent (O : Net) return Instance renames Get_Net_Parent; function Get_Port_Idx (O : Net) return Port_Idx; function Get_First_Sink (O : Net) return Input; function Get_Width (N : Net) return Width; diff --git a/src/synth/synth-environment-debug.adb b/src/synth/synth-environment-debug.adb index f4a8c719b..c92b0d73d 100644 --- a/src/synth/synth-environment-debug.adb +++ b/src/synth/synth-environment-debug.adb @@ -44,7 +44,7 @@ package body Synth.Environment.Debug is Dump_Net_Name (N); Put ("{w=" & Uns32'Image (Get_Width (N)) & '}'); Put (" := "); - Disp_Instance (Get_Parent (N), False); + Disp_Instance (Get_Net_Parent (N), False); else Put ("unassigned"); end if; @@ -108,7 +108,7 @@ package body Synth.Environment.Debug is Put (", width:" & Width'Image (Get_Width (Arec.Value))); New_Line; Put (" value: "); - Disp_Instance (Get_Parent (Arec.Value), False); + Disp_Instance (Get_Net_Parent (Arec.Value), False); Asgn := Arec.Next; end; New_Line; diff --git a/src/synth/synth-environment.adb b/src/synth/synth-environment.adb index 20b3441cd..2785d9b08 100644 --- a/src/synth/synth-environment.adb +++ b/src/synth/synth-environment.adb @@ -292,7 +292,7 @@ package body Synth.Environment is | Wire_Variable => -- Check output is not already assigned. pragma Assert - (Get_Input_Net (Get_Parent (Outport), 0) = No_Net); + (Get_Input_Net (Get_Net_Parent (Outport), 0) = No_Net); when others => raise Internal_Error; @@ -468,7 +468,7 @@ package body Synth.Environment is else Value := Build_Concatn (Ctxt, Last_Off, Uns32 (Nbr_Assign)); declare - Inst : constant Instance := Get_Parent (Value); + Inst : constant Instance := Get_Net_Parent (Value); begin Asgn := First_Assign; for I in reverse 0 .. Nbr_Assign - 1 loop @@ -483,7 +483,7 @@ package body Synth.Environment is (Ctxt : Builders.Context_Acc; Wire_Rec : Wire_Id_Record) is use Vhdl.Nodes; - Gate_Inst : constant Instance := Get_Parent (Wire_Rec.Gate); + Gate_Inst : constant Instance := Get_Net_Parent (Wire_Rec.Gate); Inp : constant Input := Get_Input (Gate_Inst, 0); Value : Net; begin diff --git a/src/synth/synth-expr.adb b/src/synth/synth-expr.adb index 4fbc5e5d3..1c085b1c8 100644 --- a/src/synth/synth-expr.adb +++ b/src/synth/synth-expr.adb @@ -977,7 +977,7 @@ package body Synth.Expr is function Is_Const (N : Net) return Boolean is begin - case Get_Id (Get_Module (Get_Parent (N))) is + case Get_Id (Get_Module (Get_Net_Parent (N))) is when Id_Const_UB32 => return True; when others => @@ -987,7 +987,7 @@ package body Synth.Expr is function Get_Const (N : Net) return Int32 is - Inst : constant Instance := Get_Parent (N); + Inst : constant Instance := Get_Net_Parent (N); begin case Get_Id (Get_Module (Inst)) is when Id_Const_UB32 => @@ -1010,7 +1010,7 @@ package body Synth.Expr is Inp := Val; loop - Inst := Get_Parent (Inp); + Inst := Get_Net_Parent (Inp); case Get_Id (Get_Module (Inst)) is when Id_Add => Val_I0 := Get_Input_Net (Inst, 0); @@ -1069,8 +1069,8 @@ package body Synth.Expr is end if; declare - Linst : constant Instance := Get_Parent (L); - Rinst : constant Instance := Get_Parent (R); + Linst : constant Instance := Get_Net_Parent (L); + Rinst : constant Instance := Get_Net_Parent (R); begin if Get_Id (Linst) /= Get_Id (Rinst) then return False; diff --git a/src/synth/synth-inference.adb b/src/synth/synth-inference.adb index b1d8c79dd..0b7327512 100644 --- a/src/synth/synth-inference.adb +++ b/src/synth/synth-inference.adb @@ -101,7 +101,7 @@ package body Synth.Inference is procedure Find_Longest_Loop (Val : Net; Prev_Val : Net; Res : out Instance; Dist : out Integer) is - Inst : constant Instance := Get_Parent (Val); + Inst : constant Instance := Get_Net_Parent (Val); begin if Get_Id (Inst) = Id_Mux2 then declare @@ -209,7 +209,7 @@ package body Synth.Inference is end if; return; end if; - Inst := Get_Parent (Els); + Inst := Get_Net_Parent (Els); if Get_Id (Inst) /= Id_Extract then raise Internal_Error; end if; @@ -256,7 +256,7 @@ package body Synth.Inference is Disconnect (I1); -- If the signal declaration has an initial value, get it. - Sig := Get_Parent (Prev_Val); + Sig := Get_Net_Parent (Prev_Val); if Get_Id (Get_Module (Sig)) = Id_Isignal then Init := Get_Input_Net (Sig, 1); Init := Build2_Extract (Ctxt, Init, Off, Get_Width (O)); @@ -472,7 +472,7 @@ package body Synth.Inference is end if; -- Latch or combinational loop. - if Get_Id (Get_Parent (Prev_Val)) = Id_Output then + if Get_Id (Get_Net_Parent (Prev_Val)) = Id_Output then -- Outputs are connected to a port. The port is the first connection -- made, so it is the last sink. Be more tolerant and look for -- the (only) port connected to the output. diff --git a/src/synth/synth-source.adb b/src/synth/synth-source.adb index d160da1f2..0ccbf0d90 100644 --- a/src/synth/synth-source.adb +++ b/src/synth/synth-source.adb @@ -25,7 +25,7 @@ package body Synth.Source is procedure Set_Location (N : Net; Src : Syn_Src) is begin if Flag_Locations then - Set_Location (Get_Parent (N), Get_Location (Src)); + Set_Location (Get_Net_Parent (N), Get_Location (Src)); end if; end Set_Location; end Synth.Source; diff --git a/src/synth/synth-stmts.adb b/src/synth/synth-stmts.adb index 985dd69db..50229d775 100644 --- a/src/synth/synth-stmts.adb +++ b/src/synth/synth-stmts.adb @@ -2145,7 +2145,7 @@ package body Synth.Stmts is Clk := Synth_PSL_Expression (Syn_Inst, Get_PSL_Clock (Stmt)); -- Check the clock is an edge and extract it. - Clk_Inst := Get_Parent (Clk); + Clk_Inst := Get_Net_Parent (Clk); if Get_Id (Clk_Inst) /= Id_Edge then Error_Msg_Synth (+Stmt, "clock is not an edge"); return No_Net; @@ -2160,7 +2160,7 @@ package body Synth.Stmts is -- For each state: if set, evaluate all outgoing edges. Next_States := Synth_Psl_NFA (Syn_Inst, Get_PSL_NFA (Stmt), Nbr_States, States); - Connect (Get_Input (Get_Parent (States), 1), Next_States); + Connect (Get_Input (Get_Net_Parent (States), 1), Next_States); -- The NFA state is correct as long as there is a 1. return Build_Reduce (Build_Context, @@ -2219,7 +2219,7 @@ package body Synth.Stmts is Clk := Synth_PSL_Expression (Syn_Inst, Get_PSL_Clock (Stmt)); -- Check the clock is an edge and extract it. - Clk_Inst := Get_Parent (Clk); + Clk_Inst := Get_Net_Parent (Clk); if Get_Id (Clk_Inst) /= Id_Edge then Error_Msg_Synth (+Stmt, "clock is not an edge"); return No_Net; @@ -2233,7 +2233,7 @@ package body Synth.Stmts is -- create update nets -- For each state: if set, evaluate all outgoing edges. Next_States := Synth_Psl_NFA (Syn_Inst, NFA, Nbr_States, States); - Connect (Get_Input (Get_Parent (States), 1), Next_States); + Connect (Get_Input (Get_Net_Parent (States), 1), Next_States); return Build_Monadic (Build_Context, Netlists.Gates.Id_Not, -- cgit v1.2.3