From 37f4aea448ae353c9ffd4254ffcc8102d6ef9f0f Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Wed, 21 Apr 2021 19:29:09 +0200 Subject: synth-vhdl_oper.adb: handle resize sgn/sgn. Fix #1731 With an hint from T.Meissner --- src/synth/synth-vhdl_oper.adb | 1 + 1 file changed, 1 insertion(+) (limited to 'src') diff --git a/src/synth/synth-vhdl_oper.adb b/src/synth/synth-vhdl_oper.adb index 0a3075b94..f741d7fc7 100644 --- a/src/synth/synth-vhdl_oper.adb +++ b/src/synth/synth-vhdl_oper.adb @@ -1961,6 +1961,7 @@ package body Synth.Vhdl_Oper is Create_Vec_Type_By_Length (W, Logic_Type)); end; when Iir_Predefined_Ieee_Numeric_Std_Resize_Sgn_Nat + | Iir_Predefined_Ieee_Numeric_Std_Resize_Sgn_Sgn | Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Vector_Sgn | Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Sgn | Iir_Predefined_Ieee_Std_Logic_Arith_Sxt => -- cgit v1.2.3