From 36b19897aea1140b0e988fed620ac2597b3b2440 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Sat, 29 Oct 2022 10:20:54 +0200 Subject: synth: fix crash in disp_verilog. Fix #2234 --- src/synth/netlists-disp_verilog.adb | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/synth/netlists-disp_verilog.adb b/src/synth/netlists-disp_verilog.adb index 1ab834fe9..93e572982 100644 --- a/src/synth/netlists-disp_verilog.adb +++ b/src/synth/netlists-disp_verilog.adb @@ -718,9 +718,14 @@ package body Netlists.Disp_Verilog is begin Val := Get_Input_Net (Mem, 1); Val_Inst := Get_Net_Parent (Val); - if Get_Id (Val_Inst) = Id_Isignal then - Val := Get_Input_Net (Val_Inst, 1); - end if; + case Get_Id (Val_Inst) is + when Id_Isignal => + Val := Get_Input_Net (Val_Inst, 1); + when Id_Signal => + Val := Get_Input_Net (Val_Inst, 0); + when others => + null; + end case; Disp_Memory_Init (Mem, Val, Data_W, Depth); end; end if; -- cgit v1.2.3