From 239f394ee7d731d96672387fd564808091914883 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Sun, 13 Dec 2020 10:12:34 +0100 Subject: synth-static_oper: handle to_stdulogic. For #1534 --- src/synth/synth-ieee-std_logic_1164.adb | 13 +++++++++++++ src/synth/synth-ieee-std_logic_1164.ads | 4 ++++ src/synth/synth-static_oper.adb | 27 ++++++++++++++++----------- 3 files changed, 33 insertions(+), 11 deletions(-) (limited to 'src') diff --git a/src/synth/synth-ieee-std_logic_1164.adb b/src/synth/synth-ieee-std_logic_1164.adb index 7249164b4..6aaaa7cdc 100644 --- a/src/synth/synth-ieee-std_logic_1164.adb +++ b/src/synth/synth-ieee-std_logic_1164.adb @@ -28,4 +28,17 @@ package body Synth.Ieee.Std_Logic_1164 is begin Write_U8 (M + Size_Type (Off), Std_Ulogic'Pos (Val)); end Write_Std_Logic; + + function Read_Bit_To_Std_Logic (M : Memory_Ptr; Off : Uns32) + return Std_Ulogic is + begin + case Read_U8 (M + Size_Type (Off)) is + when 0 => + return '0'; + when 1 => + return '1'; + when others => + raise Constraint_Error; + end case; + end Read_Bit_To_Std_Logic; end Synth.Ieee.Std_Logic_1164; diff --git a/src/synth/synth-ieee-std_logic_1164.ads b/src/synth/synth-ieee-std_logic_1164.ads index 59493fa74..d4e396c3e 100644 --- a/src/synth/synth-ieee-std_logic_1164.ads +++ b/src/synth/synth-ieee-std_logic_1164.ads @@ -43,6 +43,10 @@ package Synth.Ieee.Std_Logic_1164 is function Read_Std_Logic (M : Memory_Ptr; Off : Uns32) return Std_Ulogic; procedure Write_Std_Logic (M : Memory_Ptr; Off : Uns32; Val : Std_Ulogic); + -- Read as standard.bit and convert to std_logic. + function Read_Bit_To_Std_Logic (M : Memory_Ptr; Off : Uns32) + return Std_Ulogic; + type Table_1d is array (Std_Ulogic) of Std_Ulogic; type Table_2d is array (Std_Ulogic, Std_Ulogic) of Std_Ulogic; diff --git a/src/synth/synth-static_oper.adb b/src/synth/synth-static_oper.adb index cd1e5dc57..9f21a5619 100644 --- a/src/synth/synth-static_oper.adb +++ b/src/synth/synth-static_oper.adb @@ -825,18 +825,18 @@ package body Synth.Static_Oper is end; when Iir_Predefined_Ieee_Numeric_Std_Touns_Nat_Nat_Uns - | Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Int => + | Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Int => return Eval_To_Vector (Uns64 (Read_Discrete (Param1)), Read_Discrete (Param2), Res_Typ); when Iir_Predefined_Ieee_Numeric_Std_Tosgn_Int_Nat_Sgn - | Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Vector_Int => + | Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Vector_Int => return Eval_To_Vector (To_Uns64 (Read_Discrete (Param1)), Read_Discrete (Param2), Res_Typ); when Iir_Predefined_Ieee_Numeric_Std_Toint_Uns_Nat - | Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Integer_Uns - | Iir_Predefined_Ieee_Std_Logic_Unsigned_Conv_Integer => + | Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Integer_Uns + | Iir_Predefined_Ieee_Std_Logic_Unsigned_Conv_Integer => -- UNSIGNED to Natural. return Create_Memory_Discrete (Eval_Unsigned_To_Integer (Get_Memtyp (Param1), Expr), Res_Typ); @@ -867,6 +867,14 @@ package body Synth.Static_Oper is return Resize_Vec (Get_Memtyp (Param1), Uns32 (Read_Discrete (Param2)), False); + when Iir_Predefined_Ieee_1164_To_Stdulogic => + declare + B : Std_Ulogic; + begin + B := Read_Bit_To_Std_Logic (Param1.Val.Mem, 0); + return Create_Memory_U8 (Std_Ulogic'Pos (B), Res_Typ); + end; + when Iir_Predefined_Ieee_1164_To_Stdlogicvector_Bv => declare El_Type : constant Type_Acc := Get_Array_Element (Res_Typ); @@ -877,16 +885,13 @@ package body Synth.Static_Oper is Bnd := Create_Vec_Type_By_Length (Uns32 (Vec_Length (Param1.Typ)), El_Type); Res := Create_Memory (Bnd); - for I in 1 .. Vec_Length (Param1.Typ) loop - if Read_U8 (Param1.Val.Mem + Size_Type (I - 1)) = 0 then - B := '0'; - else - B := '1'; - end if; - Write_Std_Logic (Res.Mem, Uns32 (I - 1), B); + for I in 1 .. Uns32 (Vec_Length (Param1.Typ)) loop + B := Read_Bit_To_Std_Logic (Param1.Val.Mem, I - 1); + Write_Std_Logic (Res.Mem, I - 1, B); end loop; return Res; end; + when Iir_Predefined_Ieee_Math_Real_Log2 => declare function Log2 (Arg : Fp64) return Fp64; -- cgit v1.2.3