From 02efa5de54ddd02dfa03c644c49d8fffba5960bb Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Wed, 1 Apr 2020 08:19:35 +0200 Subject: synth-static_oper: handle mul nat uns. Fix #1179 --- src/synth/synth-ieee-numeric_std.adb | 27 +++++++++++++++++++++++++++ src/synth/synth-ieee-numeric_std.ads | 2 ++ src/synth/synth-ieee-std_logic_1164.ads | 1 + src/synth/synth-static_oper.adb | 17 +++++++++++++++++ 4 files changed, 47 insertions(+) (limited to 'src') diff --git a/src/synth/synth-ieee-numeric_std.adb b/src/synth/synth-ieee-numeric_std.adb index ca0f48362..d997c93b8 100644 --- a/src/synth/synth-ieee-numeric_std.adb +++ b/src/synth/synth-ieee-numeric_std.adb @@ -252,6 +252,33 @@ package body Synth.Ieee.Numeric_Std is return Res; end Mul_Uns_Uns; + procedure To_Unsigned (Res : out Std_Logic_Vector; Val : Uns64) + is + E : Std_Ulogic; + begin + for I in Res'Range loop + if (Shift_Right (Val, Natural (Res'Last - I)) and 1) = 0 then + E := '0'; + else + E := '1'; + end if; + Res (I) := E; + end loop; + end To_Unsigned; + + function Mul_Nat_Uns (L : Uns64; R : Std_Logic_Vector) + return Std_Logic_Vector + is + pragma Assert (R'First = 1); + T : Std_Logic_Vector (1 .. R'Last); + begin + if R'Last < 1 then + return Null_Vec; + end if; + To_Unsigned (T, L); + return Mul_Uns_Uns (T, R); + end Mul_Nat_Uns; + function Mul_Sgn_Sgn (L, R : Std_Logic_Vector) return Std_Logic_Vector is pragma Assert (L'First = 1); diff --git a/src/synth/synth-ieee-numeric_std.ads b/src/synth/synth-ieee-numeric_std.ads index 6f5b5f302..f0004c846 100644 --- a/src/synth/synth-ieee-numeric_std.ads +++ b/src/synth/synth-ieee-numeric_std.ads @@ -40,6 +40,8 @@ package Synth.Ieee.Numeric_Std is return Std_Logic_Vector; function Mul_Uns_Uns (L, R : Std_Logic_Vector) return Std_Logic_Vector; + function Mul_Nat_Uns (L : Uns64; R : Std_Logic_Vector) + return Std_Logic_Vector; function Mul_Sgn_Sgn (L, R : Std_Logic_Vector) return Std_Logic_Vector; end Synth.Ieee.Numeric_Std; diff --git a/src/synth/synth-ieee-std_logic_1164.ads b/src/synth/synth-ieee-std_logic_1164.ads index a328f6dec..14309cd42 100644 --- a/src/synth/synth-ieee-std_logic_1164.ads +++ b/src/synth/synth-ieee-std_logic_1164.ads @@ -38,6 +38,7 @@ package Synth.Ieee.Std_Logic_1164 is subtype X01 is Std_Ulogic range 'X' .. '1'; -- Vector of logic state. + -- First index is the leftest. type Std_Logic_Vector is array (Natural range <>) of Std_Ulogic; type Table_1d is array (Std_Ulogic) of Std_Ulogic; diff --git a/src/synth/synth-static_oper.adb b/src/synth/synth-static_oper.adb index 5e22fabeb..d01261213 100644 --- a/src/synth/synth-static_oper.adb +++ b/src/synth/synth-static_oper.adb @@ -453,6 +453,21 @@ package body Synth.Static_Oper is end; end Synth_Mul_Uns_Uns; + function Synth_Mul_Nat_Uns (L, R : Value_Acc; Loc : Syn_Src) + return Value_Acc + is + pragma Unreferenced (Loc); + R_Arr : Std_Logic_Vector (1 .. Natural (R.Arr.Len)); + L_Val : constant Uns64 := Uns64 (L.Scal); + begin + To_Std_Logic_Vector (R, R_Arr); + declare + Res_Arr : constant Std_Logic_Vector := Mul_Nat_Uns (L_Val, R_Arr); + begin + return To_Value_Acc (Res_Arr, R.Typ.Vec_El); + end; + end Synth_Mul_Nat_Uns; + function Synth_Mul_Sgn_Sgn (L, R : Value_Acc; Loc : Syn_Src) return Value_Acc is @@ -874,6 +889,8 @@ package body Synth.Static_Oper is when Iir_Predefined_Ieee_Numeric_Std_Mul_Uns_Uns => return Synth_Mul_Uns_Uns (Left, Right, Expr); + when Iir_Predefined_Ieee_Numeric_Std_Mul_Nat_Uns => + return Synth_Mul_Nat_Uns (Left, Right, Expr); when Iir_Predefined_Ieee_Numeric_Std_Mul_Sgn_Sgn => return Synth_Mul_Sgn_Sgn (Left, Right, Expr); -- cgit v1.2.3