From da8142e5ee6eea82e2a49a1232aeb599f0ce801d Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Wed, 10 Feb 2016 08:00:07 +0100
Subject: simul: make delayed signal elaborated.

---
 src/vhdl/simulate/elaboration.adb | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src/vhdl')

diff --git a/src/vhdl/simulate/elaboration.adb b/src/vhdl/simulate/elaboration.adb
index 571abf705..4289f24ff 100644
--- a/src/vhdl/simulate/elaboration.adb
+++ b/src/vhdl/simulate/elaboration.adb
@@ -241,6 +241,7 @@ package body Elaboration is
       T := Execute_Time_Attribute (Instance, Signal);
 
       Sig := Create_Delayed_Signal (Prefix);
+      Create_Signal (Instance, Signal);
       Instance.Objects (Info.Slot) := Sig;
 
       Init := Execute_Signal_Init_Value (Instance, Get_Prefix (Signal));
-- 
cgit v1.2.3