From 99dbf1376808a1bffb6886811d1585e34673b078 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Wed, 8 Feb 2023 11:31:04 +0100
Subject: synth: use same layout for records in memory as translate

---
 src/vhdl/vhdl-evaluation.adb | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/vhdl')

diff --git a/src/vhdl/vhdl-evaluation.adb b/src/vhdl/vhdl-evaluation.adb
index 31b44768b..45de6c827 100644
--- a/src/vhdl/vhdl-evaluation.adb
+++ b/src/vhdl/vhdl-evaluation.adb
@@ -841,7 +841,7 @@ package body Vhdl.Evaluation is
                   Res_Rng := Convert_Discrete_Range
                     (Get_Range_Constraint (Idx));
                   return Create_Vector_Type
-                    (Synth_Bounds_From_Range (Res_Rng), El_Typ);
+                    (Synth_Bounds_From_Range (Res_Rng), True, El_Typ);
                end;
 
             when others =>
-- 
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