From 8653cfdef98b6ccd591b2cdf903c4a8149a18e93 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Tue, 23 Jul 2019 18:36:50 +0200
Subject: vhdl: recognize resize function.

---
 src/vhdl/vhdl-ieee-numeric.adb | 33 +++++++++++++++++++++++++++++++++
 src/vhdl/vhdl-nodes.ads        |  5 +++++
 2 files changed, 38 insertions(+)

(limited to 'src/vhdl')

diff --git a/src/vhdl/vhdl-ieee-numeric.adb b/src/vhdl/vhdl-ieee-numeric.adb
index 9f57e7787..ad13f9274 100644
--- a/src/vhdl/vhdl-ieee-numeric.adb
+++ b/src/vhdl/vhdl-ieee-numeric.adb
@@ -319,6 +319,37 @@ package body Vhdl.Ieee.Numeric is
             raise Error;
          end if;
       end Handle_To_Integer;
+
+      procedure Handle_Resize is
+      begin
+         if Arg2_Kind = Arg_Scal and Arg2_Sign = Type_Unsigned then
+            if Arg1_Kind = Arg_Vect and Arg1_Sign = Type_Unsigned then
+               Set_Implicit_Definition
+                 (Decl, Iir_Predefined_Ieee_Numeric_Std_Resize_Uns_Nat);
+            elsif Arg1_Kind = Arg_Vect and Arg1_Sign = Type_Signed then
+               Set_Implicit_Definition
+                 (Decl, Iir_Predefined_Ieee_Numeric_Std_Resize_Sgn_Nat);
+            else
+               raise Error;
+            end if;
+         elsif Arg2_Kind = Arg_Vect then
+            if Arg1_Kind = Arg_Vect and Arg1_Sign = Type_Unsigned
+              and Arg2_Sign = Type_Unsigned
+            then
+               Set_Implicit_Definition
+                 (Decl, Iir_Predefined_Ieee_Numeric_Std_Resize_Uns_Uns);
+            elsif Arg1_Kind = Arg_Vect and Arg1_Sign = Type_Signed
+              and Arg2_Sign = Type_Signed
+            then
+               Set_Implicit_Definition
+                 (Decl, Iir_Predefined_Ieee_Numeric_Std_Resize_Sgn_Sgn);
+            else
+               raise Error;
+            end if;
+         else
+            raise Error;
+         end if;
+      end Handle_Resize;
    begin
       Decl := Get_Declaration_Chain (Pkg_Decl);
 
@@ -413,6 +444,8 @@ package body Vhdl.Ieee.Numeric is
                         Handle_To_Unsigned;
                      when Name_To_Signed =>
                         Handle_To_Signed;
+                     when Name_Resize =>
+                        Handle_Resize;
                      when others =>
                         null;
                   end case;
diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads
index c6f4a9c2a..6930d79bc 100644
--- a/src/vhdl/vhdl-nodes.ads
+++ b/src/vhdl/vhdl-nodes.ads
@@ -4886,6 +4886,11 @@ package Vhdl.Nodes is
       Iir_Predefined_Ieee_Numeric_Std_Tosgn_Int_Nat_Sgn,
       Iir_Predefined_Ieee_Numeric_Std_Tosgn_Int_Sgn_Sgn,
 
+      Iir_Predefined_Ieee_Numeric_Std_Resize_Uns_Nat,
+      Iir_Predefined_Ieee_Numeric_Std_Resize_Sgn_Nat,
+      Iir_Predefined_Ieee_Numeric_Std_Resize_Uns_Uns,
+      Iir_Predefined_Ieee_Numeric_Std_Resize_Sgn_Sgn,
+
       Iir_Predefined_Ieee_Numeric_Std_Add_Uns_Uns,
       Iir_Predefined_Ieee_Numeric_Std_Add_Uns_Nat,
       Iir_Predefined_Ieee_Numeric_Std_Add_Nat_Uns,
-- 
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