From 4111f66412d430e6770fb698870b3d0c3d1dd04f Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Fri, 18 Oct 2019 04:23:59 +0200 Subject: vhdl-prints: add parenthesis around boolean and/or. --- src/vhdl/vhdl-prints.adb | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/vhdl') diff --git a/src/vhdl/vhdl-prints.adb b/src/vhdl/vhdl-prints.adb index e24e00dbf..92fc984db 100644 --- a/src/vhdl/vhdl-prints.adb +++ b/src/vhdl/vhdl-prints.adb @@ -1841,13 +1841,17 @@ package body Vhdl.Prints is Disp_Token (Ctxt, Tok_Exclam_Mark); Print_Expr (Ctxt, Get_Boolean (N), Prio); when N_And_Bool => + Disp_Token (Ctxt, Tok_Left_Paren); Print_Expr (Ctxt, Get_Left (N), Prio); Disp_Token (Ctxt, Tok_And); Print_Expr (Ctxt, Get_Right (N), Prio); + Disp_Token (Ctxt, Tok_Right_Paren); when N_Or_Bool => + Disp_Token (Ctxt, Tok_Left_Paren); Print_Expr (Ctxt, Get_Left (N), Prio); Disp_Token (Ctxt, Tok_Or); Print_Expr (Ctxt, Get_Right (N), Prio); + Disp_Token (Ctxt, Tok_Right_Paren); when N_Imp_Bool => Print_Expr (Ctxt, Get_Left (N), Prio); Disp_Token (Ctxt, Tok_Minus_Greater); -- cgit v1.2.3