From 2416376cabc3dd03413a5038ce59ccfab569414c Mon Sep 17 00:00:00 2001
From: tmeissner <programming@goodcleanfun.de>
Date: Sat, 6 Jun 2020 13:29:57 +0200
Subject: Synthesis of PSL built-in rose() function.

---
 src/vhdl/vhdl-prints.adb   | 17 +++++++++++++++++
 src/vhdl/vhdl-sem_expr.adb |  6 +++++-
 src/vhdl/vhdl-sem_psl.adb  | 37 ++++++++++++++++++++++++++++++++++++-
 src/vhdl/vhdl-sem_psl.ads  |  1 +
 4 files changed, 59 insertions(+), 2 deletions(-)

(limited to 'src/vhdl')

diff --git a/src/vhdl/vhdl-prints.adb b/src/vhdl/vhdl-prints.adb
index a0163a63d..60da5bef2 100644
--- a/src/vhdl/vhdl-prints.adb
+++ b/src/vhdl/vhdl-prints.adb
@@ -2303,6 +2303,21 @@ package body Vhdl.Prints is
       Disp_Token (Ctxt, Tok_Right_Paren);
    end Disp_Psl_Stable;
 
+   procedure Disp_Psl_Rose (Ctxt : in out Ctxt_Class; Call : Iir)
+   is
+      Expr : Iir;
+   begin
+      Disp_Token (Ctxt, Tok_Rose);
+      Disp_Token (Ctxt, Tok_Left_Paren);
+      Print (Ctxt, Get_Expression (Call));
+      Expr := Get_Clock_Expression (Call);
+      if Expr /= Null_Iir then
+         Disp_Token (Ctxt, Tok_Comma);
+         Print (Ctxt, Expr);
+      end if;
+      Disp_Token (Ctxt, Tok_Right_Paren);
+   end Disp_Psl_Rose;
+
    procedure Disp_Psl_Declaration (Ctxt : in out Ctxt_Class; Stmt : Iir)
    is
       Decl : constant PSL_Node := Get_Psl_Declaration (Stmt);
@@ -4768,6 +4783,8 @@ package body Vhdl.Prints is
             Disp_Psl_Prev (Ctxt, Expr);
          when Iir_Kind_Psl_Stable =>
             Disp_Psl_Stable (Ctxt, Expr);
+         when Iir_Kind_Psl_Rose =>
+            Disp_Psl_Rose (Ctxt, Expr);
 
          when Iir_Kinds_Type_And_Subtype_Definition =>
             Disp_Type (Ctxt, Expr);
diff --git a/src/vhdl/vhdl-sem_expr.adb b/src/vhdl/vhdl-sem_expr.adb
index c9cc2bae6..491d9873c 100644
--- a/src/vhdl/vhdl-sem_expr.adb
+++ b/src/vhdl/vhdl-sem_expr.adb
@@ -416,7 +416,8 @@ package body Vhdl.Sem_Expr is
            | Iir_Kind_Function_Call =>
             return Expr;
          when Iir_Kind_Psl_Endpoint_Declaration
-           | Iir_Kind_Psl_Stable =>
+           | Iir_Kind_Psl_Stable
+           | Iir_Kind_Psl_Rose =>
             return Expr;
          when Iir_Kind_Simple_Name
            | Iir_Kind_Parenthesis_Name
@@ -4832,6 +4833,9 @@ package body Vhdl.Sem_Expr is
          when Iir_Kind_Psl_Stable =>
             return Sem_Psl.Sem_Stable_Builtin (Expr);
 
+         when Iir_Kind_Psl_Rose =>
+            return Sem_Psl.Sem_Rose_Builtin (Expr);
+
          when Iir_Kind_Error =>
             --  Always ok.
             --  Use the error as a type.
diff --git a/src/vhdl/vhdl-sem_psl.adb b/src/vhdl/vhdl-sem_psl.adb
index 3d36070a3..d34d36918 100644
--- a/src/vhdl/vhdl-sem_psl.adb
+++ b/src/vhdl/vhdl-sem_psl.adb
@@ -141,7 +141,7 @@ package body Vhdl.Sem_Psl is
       end if;
 
       if First then
-         --  Analyze count and clock only once.
+         --  Analyze clock only once.
          Clock := Get_Clock_Expression (Call);
          if Clock /= Null_Iir then
             Clock := Sem_Expression_Wildcard (Clock, Wildcard_Psl_Bit_Type);
@@ -158,6 +158,41 @@ package body Vhdl.Sem_Psl is
       return Call;
    end Sem_Stable_Builtin;
 
+   function Sem_Rose_Builtin (Call : Iir) return Iir
+   is
+      use Vhdl.Sem_Expr;
+      use Vhdl.Std_Package;
+      Expr  : Iir;
+      Clock : Iir;
+      First : Boolean;
+   begin
+      Expr := Get_Expression (Call);
+      First := Is_Expr_Not_Analyzed (Expr);
+      Expr := Sem_Expression (Expr, Null_Iir);
+      if Expr /= Null_Iir then
+         Set_Expression (Call, Expr);
+         Set_Type (Call, Vhdl.Std_Package.Boolean_Type_Definition);
+         Set_Expr_Staticness (Call, None);
+      end if;
+
+      if First then
+         --  Analyze clock only once.
+         Clock := Get_Clock_Expression (Call);
+         if Clock /= Null_Iir then
+            Clock := Sem_Expression_Wildcard (Clock, Wildcard_Psl_Bit_Type);
+            Set_Clock_Expression (Call, Clock);
+         else
+            if Current_Psl_Default_Clock = Null_Iir then
+               Error_Msg_Sem (+Call, "no clock for PSL rose builtin");
+            else
+               Set_Default_Clock (Call, Current_Psl_Default_Clock);
+            end if;
+         end if;
+      end if;
+
+      return Call;
+   end Sem_Rose_Builtin;
+
    --  Convert VHDL and/or/not nodes to PSL nodes.
    function Convert_Bool (Expr : Iir) return PSL_Node
    is
diff --git a/src/vhdl/vhdl-sem_psl.ads b/src/vhdl/vhdl-sem_psl.ads
index 9f13ac080..28f67ed06 100644
--- a/src/vhdl/vhdl-sem_psl.ads
+++ b/src/vhdl/vhdl-sem_psl.ads
@@ -24,6 +24,7 @@ package Vhdl.Sem_Psl is
 
    function Sem_Prev_Builtin (Call : Iir; Atype : Iir) return Iir;
    function Sem_Stable_Builtin (Call : Iir) return Iir;
+   function Sem_Rose_Builtin (Call : Iir) return Iir;
 
    procedure Sem_Psl_Declaration (Stmt : Iir);
    procedure Sem_Psl_Endpoint_Declaration (Stmt : Iir);
-- 
cgit v1.2.3