From bbdbb49e9c72b322eb2b07cd07ea164a508be7c3 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Tue, 15 Oct 2019 18:49:37 +0200 Subject: vhdl: handle cover and restrict within vunit. --- src/vhdl/vhdl-sem_psl.adb | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/vhdl/vhdl-sem_psl.adb') diff --git a/src/vhdl/vhdl-sem_psl.adb b/src/vhdl/vhdl-sem_psl.adb index e4823cd69..bd8f98b13 100644 --- a/src/vhdl/vhdl-sem_psl.adb +++ b/src/vhdl/vhdl-sem_psl.adb @@ -980,6 +980,10 @@ package body Vhdl.Sem_Psl is Item := Sem_Psl_Assert_Directive (Item, False); when Iir_Kind_Psl_Assume_Directive => Sem_Psl_Assume_Directive (Item); + when Iir_Kind_Psl_Restrict_Directive => + Sem_Psl_Restrict_Directive (Item); + when Iir_Kind_Psl_Cover_Directive => + Sem_Psl_Cover_Directive (Item); when others => Error_Kind ("sem_psl_verification_unit", Item); end case; -- cgit v1.2.3