From 0331772c3ef05bad40b748542939ccafab2a9c68 Mon Sep 17 00:00:00 2001 From: Pepijn de Vos Date: Wed, 7 Aug 2019 04:20:14 +0200 Subject: Add support for PSL assumptions, used in formal verification (#880) * vhdl: make the parser understand PSL assume * assume does not actually have report according to the spec. Just a property. * add SPL assume to semantic analysis * canonicalise PSL assume * add assume to annotations * add PSL assume to simulation code * statement -> directive * add assume to translation files * update ticked24 testcase * correctly parse assume * add assume testcase * refactor chunk of duplicated code --- src/vhdl/vhdl-scanner.adb | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/vhdl/vhdl-scanner.adb') diff --git a/src/vhdl/vhdl-scanner.adb b/src/vhdl/vhdl-scanner.adb index 740617ba4..2f08ffbab 100644 --- a/src/vhdl/vhdl-scanner.adb +++ b/src/vhdl/vhdl-scanner.adb @@ -1307,6 +1307,8 @@ package body Vhdl.Scanner is Current_Token := Tok_Psl_Property; when Std_Names.Name_Endpoint => Current_Token := Tok_Psl_Endpoint; + when Std_Names.Name_Assume => + Current_Token := Tok_Psl_Assume; when Std_Names.Name_Cover => Current_Token := Tok_Psl_Cover; when Std_Names.Name_Default => -- cgit v1.2.3