From fcd68928a4366c35748f488f949d5eada82998dd Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Mon, 19 Aug 2019 21:02:24 +0200
Subject: synth: handle verification units.

---
 src/vhdl/vhdl-parse.adb | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src/vhdl/vhdl-parse.adb')

diff --git a/src/vhdl/vhdl-parse.adb b/src/vhdl/vhdl-parse.adb
index 95b736592..95c479a57 100644
--- a/src/vhdl/vhdl-parse.adb
+++ b/src/vhdl/vhdl-parse.adb
@@ -8608,6 +8608,7 @@ package body Vhdl.Parse is
       Res : Iir;
    begin
       Res := Create_Iir (Iir_Kind_Psl_Assert_Directive);
+      Set_Location (Res);
 
       --  Accept PSL tokens
       if Flags.Vhdl_Std >= Vhdl_08 then
-- 
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