From b513a6170db4fe14eb6e885e859445d763633266 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Sat, 12 Oct 2019 07:07:42 +0200 Subject: vhdl: recognize std_logic_unsigned.conv_integer. Handle more operators in synth. --- src/vhdl/vhdl-nodes.ads | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/vhdl/vhdl-nodes.ads') diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads index bd25fb805..8de95478b 100644 --- a/src/vhdl/vhdl-nodes.ads +++ b/src/vhdl/vhdl-nodes.ads @@ -5093,6 +5093,8 @@ package Vhdl.Nodes is Iir_Predefined_Ieee_Std_Logic_Unsigned_Ne_Slv_Int, Iir_Predefined_Ieee_Std_Logic_Unsigned_Ne_Int_Slv, + Iir_Predefined_Ieee_Std_Logic_Unsigned_Conv_Integer, + -- Std_Logic_Signed (synopsys extension). Iir_Predefined_Ieee_Std_Logic_Signed_Add_Slv_Slv, Iir_Predefined_Ieee_Std_Logic_Signed_Add_Slv_Int, -- cgit v1.2.3