From b6822eff7218c6a58c3d87e8cfa4985bc3166f89 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Thu, 2 Jan 2020 09:39:01 +0100 Subject: vhdl: fix order of std_ulogic literals. For #1063 --- src/vhdl/vhdl-ieee-std_logic_1164.ads | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/vhdl/vhdl-ieee-std_logic_1164.ads') diff --git a/src/vhdl/vhdl-ieee-std_logic_1164.ads b/src/vhdl/vhdl-ieee-std_logic_1164.ads index 487fb56ff..1193bd6f7 100644 --- a/src/vhdl/vhdl-ieee-std_logic_1164.ads +++ b/src/vhdl/vhdl-ieee-std_logic_1164.ads @@ -33,9 +33,9 @@ package Vhdl.Ieee.Std_Logic_1164 is Std_Logic_0_Pos : constant := 2; Std_Logic_1_Pos : constant := 3; Std_Logic_Z_Pos : constant := 4; - Std_Logic_L_Pos : constant := 5; - Std_Logic_H_Pos : constant := 6; - Std_Logic_W_Pos : constant := 7; + Std_Logic_W_Pos : constant := 5; + Std_Logic_L_Pos : constant := 6; + Std_Logic_H_Pos : constant := 7; Std_Logic_D_Pos : constant := 8; -- Extract declarations from PKG. -- cgit v1.2.3