From 27ddfe66da98ad3ea058d29730454b19045d8621 Mon Sep 17 00:00:00 2001 From: Pepijn de Vos Date: Tue, 20 Aug 2019 19:11:10 +0200 Subject: initial support for reduce and/or (#900) --- src/vhdl/vhdl-ieee-std_logic_1164.adb | 23 ++++++++++++++++++----- 1 file changed, 18 insertions(+), 5 deletions(-) (limited to 'src/vhdl/vhdl-ieee-std_logic_1164.adb') diff --git a/src/vhdl/vhdl-ieee-std_logic_1164.adb b/src/vhdl/vhdl-ieee-std_logic_1164.adb index 58ce60769..14468e1c4 100644 --- a/src/vhdl/vhdl-ieee-std_logic_1164.adb +++ b/src/vhdl/vhdl-ieee-std_logic_1164.adb @@ -277,11 +277,24 @@ package body Vhdl.Ieee.Std_Logic_1164 is end case; Set_Implicit_Definition (Decl, Predefined); end; - elsif Is_Vector_Function (Decl) - and then Get_Identifier (Decl) = Name_Not - then - Set_Implicit_Definition - (Decl, Iir_Predefined_Ieee_1164_Vector_Not); + elsif Is_Vector_Function (Decl) then + declare + Predefined : Iir_Predefined_Functions; + begin + case Get_Identifier (Decl) is + when Name_Not => + Predefined := Iir_Predefined_Ieee_1164_Vector_Not; + when Name_And => + Predefined := + Iir_Predefined_Ieee_1164_Vector_And_Reduce; + when Name_Or => + Predefined := + Iir_Predefined_Ieee_1164_Vector_Or_Reduce; + when others => + Predefined := Iir_Predefined_None; + end case; + Set_Implicit_Definition (Decl, Predefined); + end; end if; end if; end loop; -- cgit v1.2.3