From 4870e051898d752407da802d4297d1f83bfbe433 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Tue, 27 Aug 2019 13:55:57 +0200
Subject: synth: support sequential conditional signal assignment.

Fix tgingold/ghdlsynth-beta#40
---
 src/vhdl/vhdl-annotations.adb | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src/vhdl/vhdl-annotations.adb')

diff --git a/src/vhdl/vhdl-annotations.adb b/src/vhdl/vhdl-annotations.adb
index b23e4b6e6..1e3b00043 100644
--- a/src/vhdl/vhdl-annotations.adb
+++ b/src/vhdl/vhdl-annotations.adb
@@ -872,6 +872,7 @@ package body Vhdl.Annotations is
                null;
             when Iir_Kind_Simple_Signal_Assignment_Statement
               | Iir_Kind_Selected_Waveform_Assignment_Statement
+              | Iir_Kind_Conditional_Signal_Assignment_Statement
               | Iir_Kind_Variable_Assignment_Statement =>
                null;
             when Iir_Kind_Procedure_Call_Statement =>
-- 
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