From 481c0b8d4a1045cbe192698055ff9d200d048079 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Thu, 12 Jan 2017 08:04:21 +0100 Subject: vhdl08: allow PSL default clock declaration in block declarative parts. --- src/vhdl/translate/trans-chap4.adb | 10 ++++++++++ src/vhdl/translate/trans-rtis.adb | 5 +++++ 2 files changed, 15 insertions(+) (limited to 'src/vhdl/translate') diff --git a/src/vhdl/translate/trans-chap4.adb b/src/vhdl/translate/trans-chap4.adb index 3a1cad573..32dc21136 100644 --- a/src/vhdl/translate/trans-chap4.adb +++ b/src/vhdl/translate/trans-chap4.adb @@ -1676,6 +1676,11 @@ package body Trans.Chap4 is when Iir_Kind_Disconnection_Specification => null; + when Iir_Kind_Psl_Default_Clock => + null; + when Iir_Kind_Psl_Declaration => + null; + when Iir_Kind_Component_Declaration => Chap4.Translate_Component_Declaration (Decl); when Iir_Kind_Type_Declaration => @@ -2516,6 +2521,11 @@ package body Trans.Chap4 is -- FIXME: finalizers ? Chap2.Elab_Package_Instantiation_Declaration (Decl); + when Iir_Kind_Psl_Default_Clock => + null; + when Iir_Kind_Psl_Declaration => + null; + when others => Error_Kind ("elab_declaration_chain", Decl); end case; diff --git a/src/vhdl/translate/trans-rtis.adb b/src/vhdl/translate/trans-rtis.adb index 8b191f31b..96abfc206 100644 --- a/src/vhdl/translate/trans-rtis.adb +++ b/src/vhdl/translate/trans-rtis.adb @@ -2331,6 +2331,11 @@ package body Trans.Rtis is -- FIXME: todo null; + when Iir_Kind_Psl_Default_Clock => + null; + when Iir_Kind_Psl_Declaration => + null; + when others => Error_Kind ("rti.generate_declaration_chain", Decl); end case; -- cgit v1.2.3