From 024086cfb9c965abc579aa7fb5efc3e63d39c6b5 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Sat, 1 Aug 2020 08:00:18 +0200 Subject: vhdl: parse and analyze force/release signal assignment statements. For #1416 --- src/vhdl/translate/trans-chap2.adb | 1 + src/vhdl/translate/trans-chap9.adb | 1 + src/vhdl/translate/trans_analyzes.adb | 3 +++ 3 files changed, 5 insertions(+) (limited to 'src/vhdl/translate') diff --git a/src/vhdl/translate/trans-chap2.adb b/src/vhdl/translate/trans-chap2.adb index 6d918b63a..bf704532a 100644 --- a/src/vhdl/translate/trans-chap2.adb +++ b/src/vhdl/translate/trans-chap2.adb @@ -1470,6 +1470,7 @@ package body Trans.Chap2 is | Type_Tri_State_Type | Type_Iir_Pure_State | Type_Iir_Delay_Mechanism + | Type_Iir_Force_Mode | Type_Iir_Predefined_Functions | Type_Direction_Type | Type_Iir_Int32 diff --git a/src/vhdl/translate/trans-chap9.adb b/src/vhdl/translate/trans-chap9.adb index d1bd829cb..dc59757a9 100644 --- a/src/vhdl/translate/trans-chap9.adb +++ b/src/vhdl/translate/trans-chap9.adb @@ -1382,6 +1382,7 @@ package body Trans.Chap9 is | Type_Tri_State_Type | Type_Iir_Pure_State | Type_Iir_Delay_Mechanism + | Type_Iir_Force_Mode | Type_Iir_Predefined_Functions | Type_Direction_Type | Type_Iir_Int32 diff --git a/src/vhdl/translate/trans_analyzes.adb b/src/vhdl/translate/trans_analyzes.adb index fe16b65fd..5c6e22bef 100644 --- a/src/vhdl/translate/trans_analyzes.adb +++ b/src/vhdl/translate/trans_analyzes.adb @@ -86,6 +86,9 @@ package body Trans_Analyzes is (Get_Target (Stmt), Extract_Driver_Target'Access); end if; end; + when Iir_Kind_Signal_Force_Assignment_Statement + | Iir_Kind_Signal_Release_Assignment_Statement => + null; when Iir_Kind_Conditional_Signal_Assignment_Statement => declare Cond_Wf : Iir; -- cgit v1.2.3