From 472552e574ac70d0c32746059141347c50edee55 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Tue, 20 Feb 2018 07:56:41 +0100 Subject: translation: for port assiation by expression: handle formal before actual. Fix #532 --- src/vhdl/translate/trans-chap5.adb | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/vhdl/translate/trans-chap5.adb') diff --git a/src/vhdl/translate/trans-chap5.adb b/src/vhdl/translate/trans-chap5.adb index d140a4ed0..5f8375760 100644 --- a/src/vhdl/translate/trans-chap5.adb +++ b/src/vhdl/translate/trans-chap5.adb @@ -437,11 +437,11 @@ package body Trans.Chap5 is else -- Association by value. The formal cannot be referenced in the - -- actual. + -- actual, but the type of the formal may be used by the actual. Set_Map_Env (Formal_Env); + Chap6.Translate_Signal_Name (Formal, Formal_Sig, Formal_Val); Actual_En := Chap7.Translate_Expression (Actual, Formal_Type); Actual_Sig := E2M (Actual_En, Get_Info (Formal_Type), Mode_Value); - Chap6.Translate_Signal_Name (Formal, Formal_Sig, Formal_Val); Mode := Connect_Value; -- raise Internal_Error; end if; -- cgit v1.2.3