From 53fcf00d88d1a3b34c7833aa4c421ea52f3e03dd Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Sun, 5 May 2019 07:18:49 +0200
Subject: vhdl: move sem* packages to vhdl children.

---
 src/vhdl/translate/trans-chap12.adb | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'src/vhdl/translate/trans-chap12.adb')

diff --git a/src/vhdl/translate/trans-chap12.adb b/src/vhdl/translate/trans-chap12.adb
index 1e39d3456..1659d54fb 100644
--- a/src/vhdl/translate/trans-chap12.adb
+++ b/src/vhdl/translate/trans-chap12.adb
@@ -22,8 +22,8 @@ with Std_Package; use Std_Package;
 with Iirs_Utils; use Iirs_Utils;
 with Libraries;
 with Flags;
-with Sem;
-with Sem_Lib; use Sem_Lib;
+with Vhdl.Sem;
+with Vhdl.Sem_Lib; use Vhdl.Sem_Lib;
 with Trans.Chap1;
 with Trans.Chap2;
 with Trans.Chap6;
@@ -550,7 +550,7 @@ package body Trans.Chap12 is
       if Flag_Load_All_Design_Units then
          for I in Design_Units.First .. Design_Units.Last loop
             Unit := Design_Units.Table (I);
-            Sem.Sem_Analysis_Checks_List (Unit, False);
+            Vhdl.Sem.Sem_Analysis_Checks_List (Unit, False);
             --  There cannot be remaining checks to do.
             pragma Assert
               (Get_Analysis_Checks_List (Unit) = Null_Iir_List);
-- 
cgit v1.2.3