From a3a8739ce5e5cf51e32366c8fbc6eb47ed562964 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Mon, 4 Dec 2017 04:19:13 +0100 Subject: simul: add support for case generate statetement. --- src/vhdl/simulate/simul-annotations.adb | 15 ++++++++++ src/vhdl/simulate/simul-elaboration.adb | 52 +++++++++++++++++++++++++++------ src/vhdl/simulate/simul-execution.adb | 9 +++--- src/vhdl/simulate/simul-execution.ads | 6 ++++ 4 files changed, 68 insertions(+), 14 deletions(-) (limited to 'src/vhdl/simulate') diff --git a/src/vhdl/simulate/simul-annotations.adb b/src/vhdl/simulate/simul-annotations.adb index 93984c89c..5999b694d 100644 --- a/src/vhdl/simulate/simul-annotations.adb +++ b/src/vhdl/simulate/simul-annotations.adb @@ -885,6 +885,19 @@ package body Simul.Annotations is Get_Parameter_Specification (Stmt)); end Annotate_For_Generate_Statement; + procedure Annotate_Case_Generate_Statement + (Block_Info : Sim_Info_Acc; Stmt : Iir) + is + Assoc : Iir; + begin + Assoc := Get_Case_Statement_Alternative_Chain (Stmt); + while Assoc /= Null_Iir loop + Annotate_Generate_Statement_Body + (Block_Info, Get_Associated_Block (Assoc), Null_Iir); + Assoc := Get_Chain (Assoc); + end loop; + end Annotate_Case_Generate_Statement; + procedure Annotate_Component_Instantiation_Statement (Block_Info : Sim_Info_Acc; Stmt : Iir) is @@ -936,6 +949,8 @@ package body Simul.Annotations is Annotate_If_Generate_Statement (Block_Info, El); when Iir_Kind_For_Generate_Statement => Annotate_For_Generate_Statement (Block_Info, El); + when Iir_Kind_Case_Generate_Statement => + Annotate_Case_Generate_Statement (Block_Info, El); when Iir_Kind_Psl_Default_Clock | Iir_Kind_Psl_Declaration => diff --git a/src/vhdl/simulate/simul-elaboration.adb b/src/vhdl/simulate/simul-elaboration.adb index 3b10fa6d7..d60e643af 100644 --- a/src/vhdl/simulate/simul-elaboration.adb +++ b/src/vhdl/simulate/simul-elaboration.adb @@ -1662,6 +1662,15 @@ package body Simul.Elaboration is end if; end Elaborate_Component_Instantiation; + procedure Elaborate_Generate_Statement_Body + (Instance : Block_Instance_Acc; Bod : Iir)is + begin + Elaborate_Declarative_Part + (Instance, Get_Declaration_Chain (Bod)); + Elaborate_Statement_Part + (Instance, Get_Concurrent_Statement_Chain (Bod)); + end Elaborate_Generate_Statement_Body; + -- LRM93 12.4.2 Generate Statements procedure Elaborate_If_Generate_Statement (Instance : Block_Instance_Acc; Generate : Iir_Generate_Statement) @@ -1695,10 +1704,7 @@ package body Simul.Elaboration is -- statement. Bod := Get_Generate_Statement_Body (Clause); Ninstance := Create_Block_Instance (Instance, Bod, Bod); - Elaborate_Declarative_Part - (Ninstance, Get_Declaration_Chain (Bod)); - Elaborate_Statement_Part - (Ninstance, Get_Concurrent_Statement_Chain (Bod)); + Elaborate_Generate_Statement_Body (Ninstance, Bod); exit; end if; @@ -1747,10 +1753,7 @@ package body Simul.Elaboration is -- Store index. Store (Sub_Instance.Objects (Get_Info (Iter).Slot), Index); - Elaborate_Declarative_Part - (Sub_Instance, Get_Declaration_Chain (Bod)); - Elaborate_Statement_Part - (Sub_Instance, Get_Concurrent_Statement_Chain (Bod)); + Elaborate_Generate_Statement_Body (Sub_Instance, Bod); exit when Is_Equal (Index, Bound.Right); Update_Loop_Index (Index, Bound); @@ -1758,6 +1761,33 @@ package body Simul.Elaboration is -- FIXME: destroy index ? end Elaborate_For_Generate_Statement; + procedure Elaborate_Case_Generate_Statement + (Instance : Block_Instance_Acc; Stmt : Iir) + is + Lit : Iir_Value_Literal_Acc; + Assoc : Iir; + Bod : Iir; + Ninstance : Block_Instance_Acc; + begin + Lit := Execute_Expression (Instance, Get_Expression (Stmt)); + Assoc := Get_Case_Statement_Alternative_Chain (Stmt); + + while Assoc /= Null_Iir loop + if not Get_Same_Alternative_Flag (Assoc) then + Bod := Get_Associated_Block (Assoc); + end if; + + if Is_In_Choice (Instance, Assoc, Lit) then + Ninstance := Create_Block_Instance (Instance, Bod, Bod); + Elaborate_Generate_Statement_Body (Ninstance, Bod); + return; + end if; + + Assoc := Get_Chain (Assoc); + end loop; + raise Internal_Error; + end Elaborate_Case_Generate_Statement; + procedure Elaborate_Process_Statement (Instance : Block_Instance_Acc; Stmt : Iir) is @@ -1811,6 +1841,9 @@ package body Simul.Elaboration is when Iir_Kind_For_Generate_Statement => Elaborate_For_Generate_Statement (Instance, Stmt); + when Iir_Kind_Case_Generate_Statement => + Elaborate_Case_Generate_Statement (Instance, Stmt); + when Iir_Kind_Simple_Simultaneous_Statement => Add_Characteristic_Expression (Explicit, @@ -2269,7 +2302,8 @@ package body Simul.Elaboration is Apply_Block_Configuration_To_Iterative_Generate (Stmt, Sub_Conf (I), Sub_Inst); when Iir_Kind_If_Generate_Statement - | Iir_Kind_If_Generate_Else_Clause => + | Iir_Kind_If_Generate_Else_Clause + | Iir_Kind_Case_Generate_Statement => Elaborate_Block_Configuration (Sub_Conf (I), Sub_Inst); when others => diff --git a/src/vhdl/simulate/simul-execution.adb b/src/vhdl/simulate/simul-execution.adb index c8320ecf0..e49ea69df 100644 --- a/src/vhdl/simulate/simul-execution.adb +++ b/src/vhdl/simulate/simul-execution.adb @@ -4200,11 +4200,10 @@ package body Simul.Execution is Release (Marker, Expr_Pool); end Execute_Failed_Assertion; - function Is_In_Choice - (Instance: Block_Instance_Acc; - Choice: Iir; - Expr: Iir_Value_Literal_Acc) - return Boolean + function Is_In_Choice (Instance : Block_Instance_Acc; + Choice : Iir; + Expr : Iir_Value_Literal_Acc) + return Boolean is Res : Boolean; begin diff --git a/src/vhdl/simulate/simul-execution.ads b/src/vhdl/simulate/simul-execution.ads index ac69ed8f5..8c05cee6d 100644 --- a/src/vhdl/simulate/simul-execution.ads +++ b/src/vhdl/simulate/simul-execution.ads @@ -125,6 +125,12 @@ package Simul.Execution is function Execute_Low_Limit (Bounds : Iir_Value_Literal_Acc) return Iir_Value_Literal_Acc; + -- Return True iff EXPR is covered by CHOICE. + function Is_In_Choice (Instance : Block_Instance_Acc; + Choice : Iir; + Expr : Iir_Value_Literal_Acc) + return Boolean; + function Get_Instance_By_Scope (Instance: Block_Instance_Acc; Scope: Sim_Info_Acc) return Block_Instance_Acc; -- cgit v1.2.3