From bbdbb49e9c72b322eb2b07cd07ea164a508be7c3 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Tue, 15 Oct 2019 18:49:37 +0200 Subject: vhdl: handle cover and restrict within vunit. --- src/synth/synth-stmts.adb | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/synth') diff --git a/src/synth/synth-stmts.adb b/src/synth/synth-stmts.adb index 7ebeb1a5b..292934645 100644 --- a/src/synth/synth-stmts.adb +++ b/src/synth/synth-stmts.adb @@ -2591,6 +2591,8 @@ package body Synth.Stmts is Synth_Psl_Assert_Directive (Syn_Inst, Item); when Iir_Kind_Psl_Assume_Directive => Synth_Psl_Assume_Directive (Syn_Inst, Item); + when Iir_Kind_Psl_Restrict_Directive => + Synth_Psl_Restrict_Directive (Syn_Inst, Item); when Iir_Kind_Psl_Cover_Directive => Synth_Psl_Cover_Directive (Syn_Inst, Item); when others => -- cgit v1.2.3