From 96245c0a4df7a6bc07cd8b7c15268c78c459f3b7 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Tue, 9 Nov 2021 20:54:19 +0100 Subject: vhdl: Iir_Kind_Foreign_Module is now a library unit (instead of a design unit). Also, add Iir_Kind_Foreign_Vector_Type_Definition --- src/synth/elab-vhdl_insts.adb | 2 ++ src/synth/synth-vhdl_insts.adb | 2 ++ src/synth/synthesis.adb | 19 ++++++++++--------- 3 files changed, 14 insertions(+), 9 deletions(-) (limited to 'src/synth') diff --git a/src/synth/elab-vhdl_insts.adb b/src/synth/elab-vhdl_insts.adb index f2f53bb68..aa8203045 100644 --- a/src/synth/elab-vhdl_insts.adb +++ b/src/synth/elab-vhdl_insts.adb @@ -232,6 +232,8 @@ package body Elab.Vhdl_Insts is null; when Iir_Kinds_Verification_Unit => null; + when Iir_Kind_Foreign_Module => + raise Internal_Error; end case; end if; Next (Dep_It); diff --git a/src/synth/synth-vhdl_insts.adb b/src/synth/synth-vhdl_insts.adb index 5394834ab..914b0e02a 100644 --- a/src/synth/synth-vhdl_insts.adb +++ b/src/synth/synth-vhdl_insts.adb @@ -1208,6 +1208,8 @@ package body Synth.Vhdl_Insts is null; when Iir_Kinds_Verification_Unit => null; + when Iir_Kind_Foreign_Module => + raise Internal_Error; end case; end if; Next (Dep_It); diff --git a/src/synth/synthesis.adb b/src/synth/synthesis.adb index 57d20df13..8a2f3de67 100644 --- a/src/synth/synthesis.adb +++ b/src/synth/synthesis.adb @@ -50,18 +50,19 @@ package body Synthesis is Encoding : Name_Encoding) return Module is Base : Base_Instance_Acc; + Unit : Iir; begin Base := Make_Base_Instance; - case Iir_Kinds_Design_Unit (Get_Kind (Design)) is - when Iir_Kind_Foreign_Module => - if Synth_Top_Foreign = null then - raise Internal_Error; - end if; - Synth_Top_Foreign (Base, Get_Foreign_Node (Design), Encoding); - when Iir_Kind_Design_Unit => - Synth_Top_Entity (Base, Design, Encoding, Inst); - end case; + Unit := Get_Library_Unit (Design); + if Get_Kind (Unit) = Iir_Kind_Foreign_Module then + if Synth_Top_Foreign = null then + raise Internal_Error; + end if; + Synth_Top_Foreign (Base, Get_Foreign_Node (Unit), Encoding); + else + Synth_Top_Entity (Base, Design, Encoding, Inst); + end if; Synth.Vhdl_Insts.Synth_All_Instances; -- cgit v1.2.3