From 8ada97528f410837465f61128fadda39d2c854ee Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Thu, 15 Sep 2022 03:13:23 +0200 Subject: synth: handle access subtypes --- src/synth/elab-vhdl_types.adb | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'src/synth') diff --git a/src/synth/elab-vhdl_types.adb b/src/synth/elab-vhdl_types.adb index 33b5feb8c..8aeb33d37 100644 --- a/src/synth/elab-vhdl_types.adb +++ b/src/synth/elab-vhdl_types.adb @@ -617,6 +617,14 @@ package body Elab.Vhdl_Types is (Syn_Inst, Get_Range_Constraint (Atype)); return Create_Float_Type (Rng); end; + when Iir_Kind_Access_Subtype_Definition => + declare + Acc_Typ : Type_Acc; + begin + Acc_Typ := Synth_Subtype_Indication + (Syn_Inst, Get_Designated_Type (Atype)); + return Create_Access_Type (Acc_Typ); + end; when others => Vhdl.Errors.Error_Kind ("synth_subtype_indication", Atype); end case; -- cgit v1.2.3