From 86fd1ab3079b50c5b7234db2cedf3d1e8c0f081b Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Mon, 1 Nov 2021 19:50:19 +0100
Subject: synth: do full elaboration before synthesis

---
 src/synth/synth-vhdl_aggr.adb | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

(limited to 'src/synth/synth-vhdl_aggr.adb')

diff --git a/src/synth/synth-vhdl_aggr.adb b/src/synth/synth-vhdl_aggr.adb
index fe7e95058..6ba9fda0d 100644
--- a/src/synth/synth-vhdl_aggr.adb
+++ b/src/synth/synth-vhdl_aggr.adb
@@ -26,11 +26,12 @@ with Netlists.Builders; use Netlists.Builders;
 with Vhdl.Errors; use Vhdl.Errors;
 with Vhdl.Utils; use Vhdl.Utils;
 
-with Synth.Memtype; use Synth.Memtype;
+with Elab.Memtype; use Elab.Memtype;
+with Elab.Vhdl_Types; use Elab.Vhdl_Types;
+
 with Synth.Errors; use Synth.Errors;
 with Synth.Vhdl_Expr; use Synth.Vhdl_Expr;
-with Synth.Vhdl_Stmts; use Synth.Vhdl_Stmts;
-with Synth.Vhdl_Decls; use Synth.Vhdl_Decls;
+with Synth.Vhdl_Context; use Synth.Vhdl_Context;
 
 package body Synth.Vhdl_Aggr is
    type Stride_Array is array (Dim_Type range <>) of Nat32;
-- 
cgit v1.2.3