From f1046168bd29e08372159d99768ce9e8a014f61a Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Sat, 16 Nov 2019 11:28:20 +0100 Subject: synth: handle static mul uns uns. Fix bit order for add. --- src/synth/synth-static_oper.adb | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'src/synth/synth-static_oper.adb') diff --git a/src/synth/synth-static_oper.adb b/src/synth/synth-static_oper.adb index 645456db0..76c653329 100644 --- a/src/synth/synth-static_oper.adb +++ b/src/synth/synth-static_oper.adb @@ -138,6 +138,22 @@ package body Synth.Static_Oper is end; end Synth_Add_Uns_Nat; + function Synth_Mul_Uns_Uns (L, R : Value_Acc; Loc : Syn_Src) + return Value_Acc + is + pragma Unreferenced (Loc); + L_Arr : Std_Logic_Vector (1 .. Natural (L.Arr.Len)); + R_Arr : Std_Logic_Vector (1 .. Natural (R.Arr.Len)); + begin + To_Std_Logic_Vector (L, L_Arr); + To_Std_Logic_Vector (R, R_Arr); + declare + Res_Arr : constant Std_Logic_Vector := Mul_Uns_Uns (L_Arr, R_Arr); + begin + return To_Value_Acc (Res_Arr, L.Typ.Vec_El); + end; + end Synth_Mul_Uns_Uns; + function Synth_Static_Dyadic_Predefined (Syn_Inst : Synth_Instance_Acc; Imp : Node; Left : Value_Acc; @@ -242,6 +258,9 @@ package body Synth.Static_Oper is when Iir_Predefined_Ieee_Numeric_Std_Add_Uns_Nat => return Synth_Add_Uns_Nat (Left, Right, Expr); + when Iir_Predefined_Ieee_Numeric_Std_Mul_Uns_Uns => + return Synth_Mul_Uns_Uns (Left, Right, Expr); + when others => Error_Msg_Synth (+Expr, "synth_static_dyadic_predefined: unhandled " -- cgit v1.2.3