From f7f0f0a48f49e0328401c1f60575f07c92c0c15f Mon Sep 17 00:00:00 2001 From: Pepijn de Vos Date: Thu, 15 Aug 2019 09:59:45 +0200 Subject: add synthesis support for logic operators on numeric types (#893) * add logic operators on unsigned * handle signed too * handle unary not --- src/synth/synth-disp_vhdl.adb | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'src/synth/synth-disp_vhdl.adb') diff --git a/src/synth/synth-disp_vhdl.adb b/src/synth/synth-disp_vhdl.adb index e7d61b11c..2abd0da44 100644 --- a/src/synth/synth-disp_vhdl.adb +++ b/src/synth/synth-disp_vhdl.adb @@ -25,6 +25,7 @@ with Name_Table; with Vhdl.Prints; with Vhdl.Std_Package; with Vhdl.Ieee.Std_Logic_1164; +with Vhdl.Ieee.Numeric; with Vhdl.Errors; use Vhdl.Errors; with Vhdl.Utils; use Vhdl.Utils; @@ -101,6 +102,16 @@ package body Synth.Disp_Vhdl is end if; Put_Line (";"); Idx := Idx + 1; + elsif Btype = Vhdl.Ieee.Numeric.Numeric_Std_Unsigned_Type + or Btype = Vhdl.Ieee.Numeric.Numeric_Std_Signed_Type then + Put (" wrap_" & Pfx & " <= std_logic_vector(" & Pfx); + if Desc.W = 1 then + -- This is an array of length 1. A scalar is used in the + -- netlist. + Put (" (" & Pfx & "'left)"); + end if; + Put_Line (");"); + Idx := Idx + 1; else Error_Kind ("disp_in_converter(arr)", Ptype); end if; -- cgit v1.2.3