From 8c7b05c79661cd140305c214de9b00747042723c Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Mon, 5 Aug 2019 08:09:00 +0200 Subject: synth: improve support of vhdl08. Fix #882 --- src/synth/synth-decls.adb | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) (limited to 'src/synth/synth-decls.adb') diff --git a/src/synth/synth-decls.adb b/src/synth/synth-decls.adb index b31e2c1cb..53a5b0c5f 100644 --- a/src/synth/synth-decls.adb +++ b/src/synth/synth-decls.adb @@ -205,10 +205,19 @@ package body Synth.Decls is Etyp : Type_Acc; Bnds : Bound_Array_Acc; begin - -- LRM93 12.3.1.3 - -- The elaboration of an index constraint consists of the - -- declaration of each of the discrete ranges in the index - -- constraint in some order that is not defined by the language. + -- VHDL08 + if Get_Array_Element_Constraint (Atype) /= Null_Node + or else + (Get_Resolution_Indication (Atype) /= Null_Node + and then + (Get_Kind (Get_Resolution_Indication (Atype)) + = Iir_Kind_Array_Element_Resolution)) + then + -- This subtype has created a new anonymous subtype for the + -- element. + Synth_Subtype_Indication (Syn_Inst, El_Type); + end if; + Etyp := Get_Value_Type (Syn_Inst, El_Type); if Etyp.Kind = Type_Bit -- cgit v1.2.3