From ec43db0fb7543b62ab9d326e978cceb70defe58e Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Fri, 28 Jun 2019 19:08:32 +0200
Subject: synth: disp_vhdl: merge literals.

---
 src/synth/netlists-utils.adb | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

(limited to 'src/synth/netlists-utils.adb')

diff --git a/src/synth/netlists-utils.adb b/src/synth/netlists-utils.adb
index 0f33002d3..1b8d08b1a 100644
--- a/src/synth/netlists-utils.adb
+++ b/src/synth/netlists-utils.adb
@@ -18,6 +18,8 @@
 --  Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
 --  MA 02110-1301, USA.
 
+with Netlists.Gates;
+
 package body Netlists.Utils is
    function Get_Nbr_Inputs (Inst : Instance) return Port_Nbr
    is
@@ -74,6 +76,19 @@ package body Netlists.Utils is
       return Get_Driver (Get_Input (Inst, Idx));
    end Get_Input_Net;
 
+   function Is_Const (Id : Module_Id) return Boolean
+   is
+      use Netlists.Gates;
+   begin
+      case Id is
+         when Id_Const_UB32
+           | Id_Const_UL32 =>
+            return True;
+         when others =>
+            return False;
+      end case;
+   end Is_Const;
+
    function Is_Connected (O : Net) return Boolean is
    begin
       return Get_First_Sink (O) /= No_Input;
-- 
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