From 7298513634bf4a649a2737afd87e02aced87aee6 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Sun, 31 May 2020 09:19:07 +0200 Subject: synth: improve support of true dual port rams. For #1069 --- src/synth/netlists-inference.adb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/synth/netlists-inference.adb') diff --git a/src/synth/netlists-inference.adb b/src/synth/netlists-inference.adb index 91e095211..d2a749968 100644 --- a/src/synth/netlists-inference.adb +++ b/src/synth/netlists-inference.adb @@ -340,7 +340,7 @@ package body Netlists.Inference is and then Can_Infere_RAM (Data, Prev_Val) then -- Maybe it is a RAM. - Res := Infere_RAM (Ctxt, Data, Clk, Clk_Enable); + Res := Infere_RAM (Ctxt, Data, Els, Clk, Clk_Enable); else if Clk_Enable /= No_Net then -- If there is a condition with the clock, that's an enable which -- cgit v1.2.3