From c7d32abe6f8108c0e7af6eea5d546be2bd83b704 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Sun, 28 Nov 2021 18:14:34 +0100 Subject: synth memories: also accept constant signal as memory initial value --- src/synth/netlists-disp_vhdl.adb | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) (limited to 'src/synth/netlists-disp_vhdl.adb') diff --git a/src/synth/netlists-disp_vhdl.adb b/src/synth/netlists-disp_vhdl.adb index 580eec452..0b2eb9110 100644 --- a/src/synth/netlists-disp_vhdl.adb +++ b/src/synth/netlists-disp_vhdl.adb @@ -766,9 +766,14 @@ package body Netlists.Disp_Vhdl is begin Val := Get_Input_Net (Mem, 1); Val_Inst := Get_Net_Parent (Val); - if Get_Id (Val_Inst) = Id_Isignal then - Val := Get_Input_Net (Val_Inst, 1); - end if; + case Get_Id (Val_Inst) is + when Id_Isignal => + Val := Get_Input_Net (Val_Inst, 1); + when Id_Signal => + Val := Get_Input_Net (Val_Inst, 0); + when others => + null; + end case; Put (" :="); Disp_Memory_Init (Val, Data_W, Depth); end; -- cgit v1.2.3