From 7c8ed1216609d69cd6a092620d7aa1334e432fd9 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Sat, 16 Jul 2022 08:31:51 +0200
Subject: vhdl: preliminary work to elaborat quantities

---
 src/synth/elab-vhdl_insts.adb | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'src/synth/elab-vhdl_insts.adb')

diff --git a/src/synth/elab-vhdl_insts.adb b/src/synth/elab-vhdl_insts.adb
index a86c94eb1..b5c4a7bc9 100644
--- a/src/synth/elab-vhdl_insts.adb
+++ b/src/synth/elab-vhdl_insts.adb
@@ -472,6 +472,8 @@ package body Elab.Vhdl_Insts is
            | Iir_Kind_Concurrent_Conditional_Signal_Assignment
            | Iir_Kind_Concurrent_Selected_Signal_Assignment
            | Iir_Kind_Concurrent_Procedure_Call_Statement
+           | Iir_Kind_Concurrent_Break_Statement
+           | Iir_Kind_Simple_Simultaneous_Statement
            | Iir_Kinds_Process_Statement =>
             null;
          when Iir_Kind_If_Generate_Statement =>
-- 
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