From e18d42a3b9029d7210ea19b9ae343b1d0e3cde7a Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Thu, 8 Feb 2018 04:03:08 +0100 Subject: std_names: add more keywords. --- src/std_names.ads | 23 +++++++++++++---------- 1 file changed, 13 insertions(+), 10 deletions(-) (limited to 'src/std_names.ads') diff --git a/src/std_names.ads b/src/std_names.ads index b078f4b72..ff273de02 100644 --- a/src/std_names.ads +++ b/src/std_names.ads @@ -492,14 +492,12 @@ package Std_Names is Name_VITAL_Level1 : constant Name_Id := Name_First_Ieee + 010; Name_Numeric_Std : constant Name_Id := Name_First_Ieee + 011; Name_Numeric_Bit : constant Name_Id := Name_First_Ieee + 012; - Name_Unsigned : constant Name_Id := Name_First_Ieee + 013; - Name_Signed : constant Name_Id := Name_First_Ieee + 014; - Name_Unresolved_Unsigned : constant Name_Id := Name_First_Ieee + 015; - Name_Unresolved_Signed : constant Name_Id := Name_First_Ieee + 016; - Name_Std_Logic_Arith : constant Name_Id := Name_First_Ieee + 017; - Name_Std_Logic_Signed : constant Name_Id := Name_First_Ieee + 018; - Name_Std_Logic_Textio : constant Name_Id := Name_First_Ieee + 019; - Name_Std_Logic_Unsigned : constant Name_Id := Name_First_Ieee + 020; + Name_Unresolved_Unsigned : constant Name_Id := Name_First_Ieee + 013; + Name_Unresolved_Signed : constant Name_Id := Name_First_Ieee + 014; + Name_Std_Logic_Arith : constant Name_Id := Name_First_Ieee + 015; + Name_Std_Logic_Signed : constant Name_Id := Name_First_Ieee + 016; + Name_Std_Logic_Textio : constant Name_Id := Name_First_Ieee + 017; + Name_Std_Logic_Unsigned : constant Name_Id := Name_First_Ieee + 018; Name_Last_Ieee : constant Name_Id := Name_Std_Logic_Unsigned; -- Verilog keywords. @@ -580,8 +578,13 @@ package Std_Names is -- Verilog 2001 Name_First_V2001 : constant Name_Id := Name_Last_Verilog + 1; - Name_Localparam : constant Name_Id := Name_First_V2001; - Name_Last_V2001 : constant Name_Id := Name_First_V2001 + 0; + Name_Automatic : constant Name_Id := Name_First_V2001 + 0; + Name_Endgenerate : constant Name_Id := Name_First_V2001 + 1; + Name_Genvar : constant Name_Id := Name_First_V2001 + 2; + Name_Localparam : constant Name_Id := Name_First_V2001 + 3; + Name_Unsigned : constant Name_Id := Name_First_V2001 + 4; + Name_Signed : constant Name_Id := Name_First_V2001 + 5; + Name_Last_V2001 : constant Name_Id := Name_First_V2001 + 5; -- Verilog Directives. Name_First_Directive : constant Name_Id := Name_Last_V2001 + 1; -- cgit v1.2.3