From a358d58e8592316fa1421445e73531e00247744f Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Sat, 1 Aug 2020 07:36:43 +0200 Subject: vhdl: add force and release tokens. For #1416 --- src/std_names.ads | 136 +++++++++++++++++++++++++++--------------------------- 1 file changed, 68 insertions(+), 68 deletions(-) (limited to 'src/std_names.ads') diff --git a/src/std_names.ads b/src/std_names.ads index 7082f13e3..31ddfb621 100644 --- a/src/std_names.ads +++ b/src/std_names.ads @@ -176,14 +176,16 @@ package Std_Names is Name_Context : constant Name_Id := Name_First_Keyword + 099; Name_Cover : constant Name_Id := Name_First_Keyword + 100; Name_Default : constant Name_Id := Name_First_Keyword + 101; - Name_Parameter : constant Name_Id := Name_First_Keyword + 102; - Name_Property : constant Name_Id := Name_First_Keyword + 103; - Name_Restrict : constant Name_Id := Name_First_Keyword + 104; - Name_Restrict_Guarantee : constant Name_Id := Name_First_Keyword + 105; - Name_Sequence : constant Name_Id := Name_First_Keyword + 106; - Name_Vmode : constant Name_Id := Name_First_Keyword + 107; - Name_Vprop : constant Name_Id := Name_First_Keyword + 108; - Name_Vunit : constant Name_Id := Name_First_Keyword + 109; + Name_Force : constant Name_Id := Name_First_Keyword + 102; + Name_Parameter : constant Name_Id := Name_First_Keyword + 103; + Name_Property : constant Name_Id := Name_First_Keyword + 104; + Name_Release : constant Name_Id := Name_First_Keyword + 105; + Name_Restrict : constant Name_Id := Name_First_Keyword + 106; + Name_Restrict_Guarantee : constant Name_Id := Name_First_Keyword + 107; + Name_Sequence : constant Name_Id := Name_First_Keyword + 108; + Name_Vmode : constant Name_Id := Name_First_Keyword + 109; + Name_Vprop : constant Name_Id := Name_First_Keyword + 110; + Name_Vunit : constant Name_Id := Name_First_Keyword + 111; Name_Last_Vhdl08 : constant Name_Id := Name_Vunit; subtype Name_Id_Vhdl08_Reserved_Words is @@ -234,66 +236,64 @@ package Std_Names is Name_Endspecify : constant Name_Id := Name_First_Verilog + 16; Name_Endtable : constant Name_Id := Name_First_Verilog + 17; Name_Endtask : constant Name_Id := Name_First_Verilog + 18; - Name_Force : constant Name_Id := Name_First_Verilog + 19; - Name_Forever : constant Name_Id := Name_First_Verilog + 20; - Name_Fork : constant Name_Id := Name_First_Verilog + 21; - Name_Highz0 : constant Name_Id := Name_First_Verilog + 22; - Name_Highz1 : constant Name_Id := Name_First_Verilog + 23; - Name_Ifnone : constant Name_Id := Name_First_Verilog + 24; - Name_Initial : constant Name_Id := Name_First_Verilog + 25; - Name_Input : constant Name_Id := Name_First_Verilog + 26; - Name_Join : constant Name_Id := Name_First_Verilog + 27; - Name_Large : constant Name_Id := Name_First_Verilog + 28; - Name_Macromodule : constant Name_Id := Name_First_Verilog + 29; - Name_Medium : constant Name_Id := Name_First_Verilog + 30; - Name_Module : constant Name_Id := Name_First_Verilog + 31; - Name_Negedge : constant Name_Id := Name_First_Verilog + 32; - Name_Nmos : constant Name_Id := Name_First_Verilog + 33; - Name_Notif0 : constant Name_Id := Name_First_Verilog + 34; - Name_Notif1 : constant Name_Id := Name_First_Verilog + 35; - Name_Output : constant Name_Id := Name_First_Verilog + 36; - Name_Pmos : constant Name_Id := Name_First_Verilog + 37; - Name_Posedge : constant Name_Id := Name_First_Verilog + 38; - Name_Primitive : constant Name_Id := Name_First_Verilog + 39; - Name_Pull0 : constant Name_Id := Name_First_Verilog + 40; - Name_Pull1 : constant Name_Id := Name_First_Verilog + 41; - Name_Pulldown : constant Name_Id := Name_First_Verilog + 42; - Name_Pullup : constant Name_Id := Name_First_Verilog + 43; - Name_Realtime : constant Name_Id := Name_First_Verilog + 44; - Name_Release : constant Name_Id := Name_First_Verilog + 45; - Name_Reg : constant Name_Id := Name_First_Verilog + 46; - Name_Repeat : constant Name_Id := Name_First_Verilog + 47; - Name_Rcmos : constant Name_Id := Name_First_Verilog + 48; - Name_Rnmos : constant Name_Id := Name_First_Verilog + 49; - Name_Rpmos : constant Name_Id := Name_First_Verilog + 50; - Name_Rtran : constant Name_Id := Name_First_Verilog + 51; - Name_Rtranif0 : constant Name_Id := Name_First_Verilog + 52; - Name_Rtranif1 : constant Name_Id := Name_First_Verilog + 53; - Name_Scalared : constant Name_Id := Name_First_Verilog + 54; - Name_Small : constant Name_Id := Name_First_Verilog + 55; - Name_Specify : constant Name_Id := Name_First_Verilog + 56; - Name_Specparam : constant Name_Id := Name_First_Verilog + 57; - Name_Strong0 : constant Name_Id := Name_First_Verilog + 58; - Name_Strong1 : constant Name_Id := Name_First_Verilog + 59; - Name_Supply0 : constant Name_Id := Name_First_Verilog + 60; - Name_Supply1 : constant Name_Id := Name_First_Verilog + 61; - Name_Tablex : constant Name_Id := Name_First_Verilog + 62; - Name_Task : constant Name_Id := Name_First_Verilog + 63; - Name_Tran : constant Name_Id := Name_First_Verilog + 64; - Name_Tranif0 : constant Name_Id := Name_First_Verilog + 65; - Name_Tranif1 : constant Name_Id := Name_First_Verilog + 66; - Name_Tri : constant Name_Id := Name_First_Verilog + 67; - Name_Tri0 : constant Name_Id := Name_First_Verilog + 68; - Name_Tri1 : constant Name_Id := Name_First_Verilog + 69; - Name_Triand : constant Name_Id := Name_First_Verilog + 70; - Name_Trior : constant Name_Id := Name_First_Verilog + 71; - Name_Trireg : constant Name_Id := Name_First_Verilog + 72; - Name_Vectored : constant Name_Id := Name_First_Verilog + 73; - Name_Wand : constant Name_Id := Name_First_Verilog + 74; - Name_Weak0 : constant Name_Id := Name_First_Verilog + 75; - Name_Weak1 : constant Name_Id := Name_First_Verilog + 76; - Name_Wire : constant Name_Id := Name_First_Verilog + 77; - Name_Wor : constant Name_Id := Name_First_Verilog + 78; + Name_Forever : constant Name_Id := Name_First_Verilog + 19; + Name_Fork : constant Name_Id := Name_First_Verilog + 20; + Name_Highz0 : constant Name_Id := Name_First_Verilog + 21; + Name_Highz1 : constant Name_Id := Name_First_Verilog + 22; + Name_Ifnone : constant Name_Id := Name_First_Verilog + 23; + Name_Initial : constant Name_Id := Name_First_Verilog + 24; + Name_Input : constant Name_Id := Name_First_Verilog + 25; + Name_Join : constant Name_Id := Name_First_Verilog + 26; + Name_Large : constant Name_Id := Name_First_Verilog + 27; + Name_Macromodule : constant Name_Id := Name_First_Verilog + 28; + Name_Medium : constant Name_Id := Name_First_Verilog + 29; + Name_Module : constant Name_Id := Name_First_Verilog + 30; + Name_Negedge : constant Name_Id := Name_First_Verilog + 31; + Name_Nmos : constant Name_Id := Name_First_Verilog + 32; + Name_Notif0 : constant Name_Id := Name_First_Verilog + 33; + Name_Notif1 : constant Name_Id := Name_First_Verilog + 34; + Name_Output : constant Name_Id := Name_First_Verilog + 35; + Name_Pmos : constant Name_Id := Name_First_Verilog + 36; + Name_Posedge : constant Name_Id := Name_First_Verilog + 37; + Name_Primitive : constant Name_Id := Name_First_Verilog + 38; + Name_Pull0 : constant Name_Id := Name_First_Verilog + 39; + Name_Pull1 : constant Name_Id := Name_First_Verilog + 40; + Name_Pulldown : constant Name_Id := Name_First_Verilog + 41; + Name_Pullup : constant Name_Id := Name_First_Verilog + 42; + Name_Realtime : constant Name_Id := Name_First_Verilog + 43; + Name_Reg : constant Name_Id := Name_First_Verilog + 44; + Name_Repeat : constant Name_Id := Name_First_Verilog + 45; + Name_Rcmos : constant Name_Id := Name_First_Verilog + 46; + Name_Rnmos : constant Name_Id := Name_First_Verilog + 47; + Name_Rpmos : constant Name_Id := Name_First_Verilog + 48; + Name_Rtran : constant Name_Id := Name_First_Verilog + 49; + Name_Rtranif0 : constant Name_Id := Name_First_Verilog + 50; + Name_Rtranif1 : constant Name_Id := Name_First_Verilog + 51; + Name_Scalared : constant Name_Id := Name_First_Verilog + 52; + Name_Small : constant Name_Id := Name_First_Verilog + 53; + Name_Specify : constant Name_Id := Name_First_Verilog + 54; + Name_Specparam : constant Name_Id := Name_First_Verilog + 55; + Name_Strong0 : constant Name_Id := Name_First_Verilog + 56; + Name_Strong1 : constant Name_Id := Name_First_Verilog + 57; + Name_Supply0 : constant Name_Id := Name_First_Verilog + 58; + Name_Supply1 : constant Name_Id := Name_First_Verilog + 59; + Name_Tablex : constant Name_Id := Name_First_Verilog + 60; + Name_Task : constant Name_Id := Name_First_Verilog + 61; + Name_Tran : constant Name_Id := Name_First_Verilog + 62; + Name_Tranif0 : constant Name_Id := Name_First_Verilog + 63; + Name_Tranif1 : constant Name_Id := Name_First_Verilog + 64; + Name_Tri : constant Name_Id := Name_First_Verilog + 65; + Name_Tri0 : constant Name_Id := Name_First_Verilog + 66; + Name_Tri1 : constant Name_Id := Name_First_Verilog + 67; + Name_Triand : constant Name_Id := Name_First_Verilog + 68; + Name_Trior : constant Name_Id := Name_First_Verilog + 69; + Name_Trireg : constant Name_Id := Name_First_Verilog + 70; + Name_Vectored : constant Name_Id := Name_First_Verilog + 71; + Name_Wand : constant Name_Id := Name_First_Verilog + 72; + Name_Weak0 : constant Name_Id := Name_First_Verilog + 73; + Name_Weak1 : constant Name_Id := Name_First_Verilog + 74; + Name_Wire : constant Name_Id := Name_First_Verilog + 75; + Name_Wor : constant Name_Id := Name_First_Verilog + 76; Name_Last_Verilog : constant Name_Id := Name_Wor; -- Verilog 2001 -- cgit v1.2.3