From 2b3a1bb316317453d4e40bc3a650b4ed07eee7a8 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Sat, 7 Sep 2019 17:41:00 +0200 Subject: vhdl: recognize numeric_std shift_left. --- src/std_names.ads | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'src/std_names.ads') diff --git a/src/std_names.ads b/src/std_names.ads index e20db31a9..3af9e6082 100644 --- a/src/std_names.ads +++ b/src/std_names.ads @@ -723,9 +723,11 @@ package Std_Names is Name_To_Signed : constant Name_Id := Name_First_Ieee + 021; Name_Resize : constant Name_Id := Name_First_Ieee + 022; Name_Std_Match : constant Name_Id := Name_First_Ieee + 023; - Name_Math_Real : constant Name_Id := Name_First_Ieee + 024; - Name_Ceil : constant Name_Id := Name_First_Ieee + 025; - Name_Log2 : constant Name_Id := Name_First_Ieee + 026; + Name_Shift_Left : constant Name_Id := Name_First_Ieee + 024; + Name_Shift_Right : constant Name_Id := Name_First_Ieee + 025; + Name_Math_Real : constant Name_Id := Name_First_Ieee + 026; + Name_Ceil : constant Name_Id := Name_First_Ieee + 027; + Name_Log2 : constant Name_Id := Name_First_Ieee + 028; Name_Last_Ieee : constant Name_Id := Name_Log2; -- Verilog Directives. -- cgit v1.2.3