From dfbc41e9850441a26a678c400d1e2e19491a68e6 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Sun, 8 Jan 2023 10:30:26 +0100 Subject: simul: set assertion hook before elaboration --- src/simul/simul-vhdl_simul.adb | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/simul') diff --git a/src/simul/simul-vhdl_simul.adb b/src/simul/simul-vhdl_simul.adb index 3bc859f41..5764fe5e3 100644 --- a/src/simul/simul-vhdl_simul.adb +++ b/src/simul/simul-vhdl_simul.adb @@ -4048,6 +4048,9 @@ package body Simul.Vhdl_Simul is Elab.Debugger.Debug_Elab (Vhdl_Elab.Top_Instance); end if; + Grt.Errors.Set_Error_Stream (Grt.Stdio.stdout); + Assertion_Report_Handler := Assertion_Report_Msg'Access; + Status := Grt.Main.Run_Through_Longjump (Grt.Processes.Simulation_Init'Access); @@ -4056,9 +4059,6 @@ package body Simul.Vhdl_Simul is Grt.Analog_Solver.Start; end if; - Grt.Errors.Set_Error_Stream (Grt.Stdio.stdout); - Assertion_Report_Handler := Assertion_Report_Msg'Access; - pragma Assert (Areapools.Is_Empty (Expr_Pool)); pragma Assert (Areapools.Is_Empty (Process_Pool)); -- cgit v1.2.3