From d85cb9909f6bf425cf444341fbea7d8b02c9334b Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Sat, 7 Jan 2023 13:40:13 +0100
Subject: simul: improve error recovery during elaboration

---
 src/simul/simul-vhdl_elab.adb | 15 ++++++++++++---
 1 file changed, 12 insertions(+), 3 deletions(-)

(limited to 'src/simul')

diff --git a/src/simul/simul-vhdl_elab.adb b/src/simul/simul-vhdl_elab.adb
index 77f3bc0b3..95c144473 100644
--- a/src/simul/simul-vhdl_elab.adb
+++ b/src/simul/simul-vhdl_elab.adb
@@ -188,9 +188,15 @@ package body Simul.Vhdl_Elab is
       Mark_Expr_Pool (Marker);
 
       Synth.Vhdl_Stmts.Synth_Assignment_Prefix (Inst, Name, Base, Typ, Off);
-      Res := (Base => Base.Val.S,
-              Typ => Unshare (Typ, Global_Pool'Access),
-              Offs => Off);
+      if Base = No_Valtyp then
+         Res := (Base => No_Signal_Index,
+                 Typ => null,
+                 Offs => No_Value_Offsets);
+      else
+         Res := (Base => Base.Val.S,
+                 Typ => Unshare (Typ, Global_Pool'Access),
+                 Offs => Off);
+      end if;
 
       Release_Expr_Pool (Marker);
       return Res;
@@ -565,6 +571,9 @@ package body Simul.Vhdl_Elab is
          exit when El = Null_Node;
          Sig := Compute_Sub_Signal (Inst, El);
 
+         --  Exit now in case of error.
+         exit when Sig.Base = No_Signal_Index;
+
          Sensitivity_Table.Append
            ((Sig => Sig,
              Prev_Sig => Signals_Table.Table (Sig.Base).Sensitivity,
-- 
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