From 7286838d5caaa764c7201c82fe390483ef5c5661 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Mon, 9 Jan 2023 19:05:40 +0100 Subject: synth-vhdl_aggr: optimize common aggregate --- src/simul/simul-vhdl_elab.adb | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) (limited to 'src/simul') diff --git a/src/simul/simul-vhdl_elab.adb b/src/simul/simul-vhdl_elab.adb index 849553d01..423862f6e 100644 --- a/src/simul/simul-vhdl_elab.adb +++ b/src/simul/simul-vhdl_elab.adb @@ -157,12 +157,14 @@ package body Simul.Vhdl_Elab is if E.Kind in Mode_Signal_User then if E.Typ.W > 0 then - E.Nbr_Sources := - new Nbr_Sources_Array'(0 .. E.Typ.W - 1 => - (Nbr_Drivers => 0, - Nbr_Conns => 0, - Total => 0, - Last_Proc => No_Process_Index)); + E.Nbr_Sources := new Nbr_Sources_Array (0 .. E.Typ.W - 1); + -- Avoid aggregate to avoid stack overflow. + for I in E.Nbr_Sources'Range loop + E.Nbr_Sources (I) := (Nbr_Drivers => 0, + Nbr_Conns => 0, + Total => 0, + Last_Proc => No_Process_Index); + end loop; Mark_Resolved_Signals (0, Get_Type (E.Decl), E.Typ, E.Nbr_Sources.all, False); -- cgit v1.2.3