From 7052ac9006b145c0cd51f2bad8e088c1338f3846 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Sat, 14 Jan 2023 09:42:00 +0100
Subject: synth: improve error propagation on slices

---
 src/simul/simul-vhdl_elab.adb | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

(limited to 'src/simul')

diff --git a/src/simul/simul-vhdl_elab.adb b/src/simul/simul-vhdl_elab.adb
index 0ff4d2446..69c81be35 100644
--- a/src/simul/simul-vhdl_elab.adb
+++ b/src/simul/simul-vhdl_elab.adb
@@ -536,7 +536,10 @@ package body Simul.Vhdl_Elab is
          exit when El = Null_Node;
          Sig := Compute_Sub_Signal (Inst, El);
 
-         Add_Process_Driver (Proc_Idx, Sig, El);
+         if Sig.Base /= No_Signal_Index then
+            --  Only if no error.
+            Add_Process_Driver (Proc_Idx, Sig, El);
+         end if;
 
          Next (It);
       end loop;
-- 
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